基于单片机的晶闸管触发器的设计与实现

设计了一种集同步电压检测、移相延迟角定时环节、触发脉冲时序分配等功能于一身的单片机控制的晶闸管触发器。采用软件实现了定时/计数、触发脉冲分配、双窄脉冲形成等功能。采用AT89C2051单片机实现三相全控桥式电路晶闸管的移相触发控制,降低了对单片机资源的需求。提出了用一个同步电压信号,通过触发脉冲延迟角的调整算法,实现了对称三相触发脉冲输出。设计中采用定时器计时同步方式,消除了干扰信号的影响,保证了三相桥式全控整流系统可靠工作。     

一种面向光收发器的ps级光脉冲产生器

由于高速光开关在光互连通信中越来越广泛的应用,光开关的开关速度直接影响了整个光链路的传输速率,因此对驱动光开关产生长周期窄脉冲光信号的驱动电路的性能及集成度有了更高要求。基于光电集成工艺和高速光脉冲队列技术的发展,提出了一种应用于光SerDes收发器的集成ps级窄脉冲光信号产生器。该产生器为CMOS电路产生脉宽精确可调的长周期窄脉冲,在SMIC 0.13μm CMOS工艺下可获得窄至25ps的脉冲输出,其电源电压范围宽达1.4V~2.5V,时钟频率也可由数kHz到4GHz,同时可移植到不同的CMOS工艺平台。     

基于8052单片机的三相全控桥式整流移相触发电路的实现

该文介绍了基于8052单片机实现三相全控桥式整流电路中晶闸管移相触发的方法。三相全控桥通常有单宽脉冲触发和双窄脉冲触发两种方式,该方案采用双窄脉冲触发方式,克服了单宽脉冲触发方式所带来的缺点。还采用了中断查询方法来查询过零点出现的时刻,从而获得了满足技术要求的触发脉冲。     

65 nm CMOS可集成ps级窄脉冲驱动器

光电集成工艺和高速光脉冲队列技术的发展使得新型光互连技术——光SerDes收发器得以提出。相比现有光互连技术,光SerDes技术具有更高速率、更低功耗和更高集成度的优点。但其对于驱动光开关产生长周期窄脉冲光信号的驱动电路的性能、工艺及集成度有了更高要求。提出了一种应用于光SerDes收发器的65nm CMOS工艺下的集成ps级窄脉冲驱动器。该驱动器可产生脉宽精确可调的长周期窄脉冲,可获得窄至13ps的脉冲输出,其工作电压范围宽达1.4~2.0V,时钟频率范围可由数KHz宽至25GHz。     

用EPROM构成的多种步进电机驱动电源

步进电机驱动电源的核心是环形脉冲分配器.用EPROM构成环形脉冲分配器,配以外围电路便可构成一台多种步进电机驱动电源.它的主要特点是适用于各种相数的步进电机,可在整步或半步方式下工作.可与微机直接连接,接口简单,采用TTL电平.     

用R-S触发器做受控门

<正> 在数字电路的设计中,经常碰到对时钟脉冲进行选通的问题。人们常用图1所示的受控门电路来解决。在图1的电路中,当控制端为高电平时,通过G_1反相;使G_2门处于关门状态,时钟脉冲不能通过G_2输出:当控制端为低电平时,G_2门处于开门状态,时钟脉冲被允许通过G_2输出。从面达到选通的目的。这种电路一般用在要求不太高的场合。因为在控制电平跳变时,在G_2的输出端可能会产生窄脉冲。从图2中的CP—1输出脉冲可以看出,第N个和第M个时钟脉冲的输出即为窄脉冲,而这个窄脉冲的宽度又是随     

一种用于高压大电流脉冲放电的晶闸管间接强触发电路

高压大电流放电技术普遍采用晶闸管串联作为电路放电的主开关,放电时如果晶闸管的导通过程较慢,则会导致芯片内部产生大量焦耳热,使晶闸管损坏;同时晶闸管在串联模式下,导通时间不一致也会导致导通较慢的晶闸管受到高电压而被击穿。针对该种复杂苛刻的工况,提出了一种可以用于高压大电流脉冲放电的晶闸管间接强触发电路,该电路利用间接光触发方式,在触发回路中,串联的晶闸管触发信号由同一个控制信号通过光纤进行控制,经过光电转换后产生强触发脉冲电流,使晶闸管同步快速可靠导通。实验结果表明,该电路可实现串联晶闸管可靠触发,晶闸管触发脉宽时间可调,放电电压为9kV,放电电流高达32kA,满足脉冲放电电源模块的应用要求。     

可将红外LED输出光信号幅度提高10倍的编码调制技术

<正> 设想将三电平边沿脉冲码中的负脉冲翻转为正,即得二电平脉冲码。取低电平为零电流时,只要脉冲占空比足够小,就可在平均电流不超过Im前提下用峰值远大于Im的窄脉冲电流驱动LED。目前市售的许多廉价红外LED器件,如TSUS5200系列等,完全允许在这种状态下工作。其发光波长也处于光纤低损耗区。作者按上述方案研制成的光纤数据传输系统,以廉价红外LED为光源,2CU器件为探测器,     

基于FPGA的晶闸管过零触发调功电路设计

本文针对传统的用模拟电路方法设计晶闸管过零触发脉冲电路的缺点,采用FPGA为核心.设计了一个8级功率可调的晶闸管过零触发电路,该电路包括三部分:过零脉冲产生;控制信号产生;负载触发脉冲产生.三相同步方波信号输入该电路后,将产生6路脉冲个数可调的过零触发信号,从而实现对负载功率的调节.文章采用Ouarts Ⅱ平台仿真,VHDL语言实现编程,电路简单实用,可靠性高.     

半导体激光器驱动电路的计算机仿真分析

直接调制的大电流窄脉宽驱动电源是半导体激光器获得高峰值功率输出的重要保证.为了研究半导体激光器驱动电路,提高系统的精度和抗干扰能力,采用计算机仿真的方法分析了半导体激光器脉冲电源基本电路和雪崩晶体管脉冲电源电路.通过仿真结果表明,脉冲电源中元件的寄生电感及串联电阻对激光器工作电流脉冲的波形影响很大.当奇生电感小时,放电电流波形的上升时间就短.可为设计半导体激光器驱动电路时,提供选取R、C、L的依据,并保证工作在欠阻尼的情况下,要获得最大的放电电流,储能电容器上的充电电压要高,使电路的串联电阻尽量要小.     

双伸位堆垛机系统调度的优化设计

以某机务段段修配件自动化立体仓库(AS/RS)为例,通过分析影响双伸位堆垛机系统运作的重要因素,提出一种基于作业时间最短的优化设计,建立相应的数学模型,并采用分区平均搜索初始种群的遗传算法对其进行验证。结果证明该优化设计有利于提高双伸位堆垛机AS/RS系统的运作效率。     

双伸位堆垛机系统调度的优化设计

以某机务段段修配件自动化立体仓库(AS/RS)为例,通过分析影响双伸位堆垛机系统运作的重要因素,提出一种基于作业时间最短的优化设计,建立相应的数学模型,并采用分区平均搜索初始种群的遗传算法对其进行验证。结果证明该优化设计有利于提高双伸位堆垛机AS/RS系统的运作效率。     

智能手机终端双操作系统间省电系统设计方案

随着移动通信终端性能的快速发展,智能手机的崛起导致便携式终端高性能和持久的矛盾愈演愈烈;同时,各层级低功耗技术的飞速发展也对终端省电系统设计提出更进一步的挑战。本文从嵌入式操作系统的角度,提出了一种基于智能手机终端双操作系统间的省电系统设计方案,并通过智能手机基带子系统和应用子系统操作状态设计及双系统间状态切换流程予以说明。     

基于小波能双重自恢复的音频数字水印算法

本文设计了一种在音频信息中加入双重图像作为数字水印,这些水印经过多种攻击能相互自恢复的算法。此算法实现了将双重图像作为数字水印嵌入到WAV音频载体中的过程,在实现过程中通过对载体进行3层小波分解,将数字水印的信息嵌入到第三层小波解的低频区,即CA3中,并对双重数字水印分别设置密钥,建立起两者间稳定的映射关系,能较好地以完成自恢复的功能。     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

基于MMA7455的抽油机加速度信息采集系统

文章提出一种基下MMA7455的抽油机加速度采集系统的设计,由于井场环境复杂,干扰信号较多,文章采用硬件滤波和算法滤波相结合的方式,较大程度地抑制井场的噪声干扰.测量的加速度再经过双重积分,得到位移,进而得到抽油机每次的冲程.     

Experience with approximate reliability-based optimization methods

Traditional reliability-based design optimization (RBDO) requires a double loop iteration process. The inner optimization loop is to find the most probable point (MPP) and the outer is the regular optimization loop to optimize the RBDO problem with reliability objectives or constraints. It is well known that the computation can be prohibitive when the associated function evaluation is expensive. As a result, many approximate RBDO methods, which convert the double loop to a single loop, have been developed. In this work, several approximate RBDO methods are coded, discussed, and tested against a double loop algorithm through four design problems.     

Design and improvement of product using intelligent function model based cost estimating

Design is one of the most important activities in new product development. While the concepts of design for manufacturability and concurrent engineering have made significant advances in integrating the design function with other areas in the firm, there are still major gaps in timely and accurate costing information available to designers. Inappropriate design could result in high redesign cost and delay in product realization. The generation of design and improvement is a time-consuming and mentally exhaustion process. It involves combining design features to generate as much potential design as possible. As not all features combinations are feasible, decision-makers have to narrow down the potential solutions and subsequently select appropriate design for further development.This research suggests an intelligent function model based cost estimating for design and improvement of product. It is composed of three steps aiming at the low cost design of the product. The first step is setting up the optimal cost which is the engineering target based on the function. The second step is estimating the current functional cost according to the unit through the function analysis for basic model and quantitative. The second step estimates the current functional cost according to the unit through the functional analysis of basic model and quantitative. In the third step, the design of a unit is reviewed according to the priority of the difference between the optimal cost and the functional cost. Arranging the unit design parameter, the best design option is set-up according to the level. Also, it was actually proved through the application of “S” company.     

基于模糊动态模型的二级倒立摆系统的分析和设计

首先给出了一种离散系统模糊动态模型的辨识方法,提出了一个衡量聚类有效性的函数,以确定模糊规则的数目,并给出一个保证模糊系统全局稳定的充分条件,在此基础上给出了模糊控制系统的设计方法,并对二级倒立摆系统进行了控制,取得了较好的效果。