Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I_DDQ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I_DDQ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I_DDQ -based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general     

Pausible clocking-based heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous and asynchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous first-in first-out (FIFO) channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshake signals to the local module clock is done in an unconventional way-the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshake signal satisfies setup and hold time constraints with respect to the local clock. In order to validate this scheme, we implemented a test chip in 0.5-μm CMOS. This chip is designed as a ring, composed of two synchronous modules, an asynchronous module, and two asynchronous FIFOs. Each module functions as a receiver to one module and a sender to another module. Test results show that the chip functions reliably up to 456 MHz     

异步Viterbi解码器同步接口的设计

提出了一种利用异步 FIFO ( First In First Out)连接异步逻辑电路与同步逻辑电路的方法 ,并设计实现了相应的异步 FIFO电路 ,作为连接异步 viterbi解码器和其他同步逻辑电路的同步接口。对异步 FIFO的级数与异步 viterbi解码器内部的时序关系进行了分析。用逻辑仿真的动态时序分析表明 ,当同步电路时钟的周期大于 130 ns时 ,具有同步接口的异步 viterbi解码器可以与同步电路正常协同工作。具有简单接口电路的异步解码器 ,既能发挥异步电路功率效率高的优点 ,而且能嵌入同步电路系统     

LCD控制器中异步电路的设计

异步电路的设计能够解决功耗、系统速度、时钟偏移等问题,成为当前VLSI研究的热点.文章提出了4级灰度LCD控制器异步电路的设计方案,通过异步控制以消除无效操作从而降低功耗,经验证平均功耗仅为同步电路的23.7%：异步电路还实现了部分显示和滚屏等功能,加快了系统响应速度.     

A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.     

Applications of asynchronous circuits

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility (EMC) properties, and a natural match with heterogeneous system timing. In this overview paper each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. Conditions for applying asynchronous circuit technology, such as the existence and availability of computer-aided design (CAD) tools, circuit libraries, and effective test approaches, are discussed briefly. Asynchronous circuits do offer advantages for many applications, and their design methods and tools are now starting to become mature     

一种适用于通信系统的异步加-选择-比较器

介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.     

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.     

Registers for Phase Difference Based Logic

A logic design style known as phase difference-based logic (PDBL) has several benefits with respect to security and testing. An existing design method for PDBL circuits has so far been lacking an important component, a register. In this paper, we present the design of a speed independent PDBL register and a timed PDBL register, which can be used in asynchronous or synchronous circuits. Comparisons are presented in terms of speed, size, and power consumption.     

Self-timing and vector processing in RSFQ digital circuittechnology

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increases, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists of two self-timed shift registers and an on-chip 8-28-GHz clock generator     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

Ultrafast time-domain technology and its application in all-optical signal processing

In this paper, we review recent advances in ultrafast optical time-domain technology with emphasis on the use in optical packet switching. In this respect, several key building blocks, including high-rate laser sources applicable to any time-division-multiplexing (TDM) application, optical logic circuits for bitwise processing, and clock-recovery circuits for timing synchronization with both synchronous and asynchronous data traffic, are described in detail. The circuits take advantage of the ultrafast nonlinear transfer function of semiconductor-based devices to operate successfully at rates beyond 10 Gb/s. We also demonstrate two more complex circuits-a header extraction unit and an exchange-bypass switch-operating at 10 Gb/s. These two units are key blocks for any general-purpose packet routing/switching application. Finally, we discuss the system perspective of all these modules and propose their possible incorporation in a packet switch architecture to provide low-level but high-speed functionalities. The goal is to perform as many operations as possible in the optical domain to increase node throughput and to alleviate the network from unwanted and expensive optical-electrical-optical conversions.     

读出电路开窗技术研究

读出电路开窗是红外焦平面和图像传感器读出电路中，用于提高图像帧频降低带宽的重要技术。该技术通过减小读出阵列的窗口尺寸，降低电路读出的数据量，从而提高帧频。介绍了两类主要的开窗模式:异步读出模式和同步读出模式。针对异步读出模式扩展性差、存在竞争冒险的问题，以及同步读出模式占用像元面积和窗口切换速度慢的问题，基于同步读出提出了一种行列控制字架构，并设计了一种用于该架构的可重复单元电路，提高了对不同面阵规格的扩展性。完成了所提出的开窗电路设计和版图设计，并对该电路进行了仿真验证。对比其他方案，文中设计实现了任意位置、最小1×1尺寸的开窗，同时解决了占用像元面积和竞争冒险问题，并提高了窗口切换速度。     

Interfacing synchronous and asynchronous modules within ahigh-speed pipeline

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst case conditions. These two factors together can lead to a significant improvement in average-case performance. The interface design is simulated using the 0.6-μm HP CMOS14B process in HSPICE     

A scannable pulse-to-static conversion register array forself-timed circuits

This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance     

无线Mesh网中的Quorum节能机制

无线Mesh网络节能问题十分重要。文章讨论的基于Quorum的节能机制对网络规模、节点密度、移动性和多跳等因素不敏感,非常适合无线Mesh网络。Quorum节能机制主要基于MANET网络环境设计。Quorum系统根据时钟同步的难易程度,可以应用于同步和异步两种工作模式。目前对Quorum节能系统的研究主要集中在能量效率优化和自适应系统方面。对于异步和同步两种模式的协同,基于Quorum机制的节能与功率控制、MAC路由结合的跨层设计,是值得尝试的课题。