Fabrication of monolithic diffractive optical elements by the use of e-beam direct write on an analog resist and a single chemically assistedion-beam-etching step

We present a method to fabricate high-quality and environmentally rugged monolithic diffractive optical elements (DOE's). Analog direct-write e-beam lithography was used to produce analog resist profiles that were transferred into their substrates by the use of chemically assisted ion-beam etching (CAIBE) in one single etching step. An iterative method was used to compensate for the proximity effect caused by electron scattering in the resist and from the substrate during the e-beam exposure. Slope-dependent differential etch rates that occur during the transfer process were characterized and compensated for. Finally, the DOE was divided into regions with different period ranges, and the exposure dosages were set to achieve even and accurate etch depths in the final element. The presented fabrication method will increase manufacturability and reduce processing time, which will result in a general cost reduction per element.     

Nanopatterning on nonplanar and fragile substrates with ice resists

Electron beam (e-beam) lithography using polymer resists is an important technology that provides the spatial resolution needed for nanodevice fabrication. But it is often desirable to pattern nonplanar structures on which polymeric resists cannot be reliably applied. Furthermore, fragile substrates, such as free-standing nanotubes or thin films, cannot tolerate the vigorous mechanical scrubbing procedures required to remove all residual traces of the polymer resist. Here we demonstrate several examples where e-beam lithography using an amorphous ice resist eliminates both of these difficulties and enables the fabrication of unique nanoscale device structures in a process we call ice lithography. (1, 2) We demonstrate the fabrication of micro- and nanostructures on the tip of atomic force microscope probes, microcantilevers, transmission electron microscopy grids, and suspended single-walled carbon nanotubes. Our results show that by using amorphous water ice as an e-beam resist, a new generation of nanodevice structures can be fabricated on nonplanar or fragile substrates.     

An optimal high contrast e-beam lithography process for the patterning of dense fin networks

There are many difficulties to overcome towards the integration of 10 nm CMOS technology. One such major challenge is to keep a tight control of the leakage current of devices while increasing the current drive at a reduced supply voltage. In this context, multi-gated structures, which are used to control the transport in ultra-thin channel (e.g. FinFET), are a promising solution. A critical step during the fabrication process of a FinFET is the patterning of dense, high aspect ratio fins. High demand is therefore placed on e-beam lithography techniques to obtain narrow, sharp, densely packed resist lines. This paper presents a detailed study on the optimum e-beam exposure process using a negative tone e-beam resist, namely Hydrogen Silsesquioxane (HSQ). The impact of the pre-exposure bake temperature, of the Tetramethyl Ammonium Hydroxide (TMAH) concentration in development solution and of development time has been investigated. The standard process uses 2.38% TMAH as a developer, samples being pre-baked on a hotplate at a temperature between 150 and 220 °C for 2 min. By using a lower pre-bake temperature of 90 °C and a more concentrated TMAH solution dosed at 25%, a seven-fold improvement of contrast can be obtained in terms of contrast values. Cross sectional SEM views show fin networks with a pitch ranging from 40 nm to 200 nm. The line profiles are steep and an excellent uniformity is obtained across the whole network, even for lines located at the edge. Dense patterns are presented with lines as narrow as 15 nm and with a 25 nm space.     

Application of auxiliary metal layers to e-beam and X-ray lithography

Micron and sub-micron gold lines have been produced by liftoff following e-beam and X-ray exposures of resist coated chromium layers on silicon. Etching a 0.1 micron chromium layer after development results in an undercut which aids the liftoff process. This approach has been used in e-beam lithography on PMMA (i.e. positive resist) to decouple the e-beam exposure from generation of the undercut. In this way 0.7 micron gold lines separated by less than 0.3 microns have been produced. A similar approach when used in X-ray lithography on OEBR (negative resist) yielded gold lines down to 0.3 microns in width and separation. Scanning electron micrographs of patterns at various stages of processing are presented and the profiles of the resist walls and the nature of the undercut are described.     

A Simplified Method to Produce a Functional Test Stamp for Nanoimprint Lithography (NIL)

Nanoimprint lithography (NIL) is a novel technique that allows fabrication of submicron features into substrates using a modified embossing method into a polymer resist. In most cases, a stamp is produced by direct e-beam writing into a resist and then the pattern is etched into the substrate. Other stamp fabrication methods exist but, in general, they are expensive to produce. When performing NIL, damage may occur to the stamp unless the process steps are optimized. In this letter, we illustrate a simple and inexpensive method to produce a test stamp to use for NIL process optimization. This may have wide applications in both industrial and academic settings.      

Combined AFM nano-machining and reactive ion etching to fabricate high aspect ratio structures

In this paper, a new combined method of sub-micron high aspect ratio structure fabrication is developed which can be used for production of nano imprint template. The process includes atomic force microscope (AFM) scratch nano-machining and reactive ion etching (RIE) fabrication. First, 40 nm aluminum film was deposited on the silicon substrate by magnetron sputtering, and then sub-micron grooves were fabricated on the aluminum film by nano scratch using AFM diamond tip. As aluminum film is a good mask for etching silicon, high aspect ratio structures were finally fabricated by RIE process. The fabricated structures were studied by SEM, which shows that the grooves are about 400 nm in width and 5 microm in depth. To obtain sub-micron scale groove structures on the aluminum film, experiments of nanomachining on aluminum films under various machining conditions were conducted. The depths of the grooves fabricated using different scratch loads were also studied by the AFM. The result shows that the material properties of the film/substrate are elastic-plastic following nearly a bilinear law with isotropic strain hardening. Combined AFM nanomachining and RIE process provides a relative lower cost nano fabrication technique than traditional e-beam lithography, and it has a good prospect in nano imprint template fabrication.     

Fabrication of metal nanostructures by atomic force microscopy nanomachining and related applications

In this work, the fabrication of metal nanostructures by a combination of atomic force microscopy nanomachining on a thin polymer resist, metal coating and lift-off is presented. Nanodots with sizes down to 20 nm and nanowires with widths ranging between 40 and 100 nm have been successfully created by nanoindenting and nanoscratching. The results exemplify the feasibility and effectiveness of the present technique as an alternative to e-beam lithography. The localized surface plasmon resonance properties of the fabricated nanostructures are characterized. The chemical sensing capability of a single nanowire based on resistance increase is also demonstrated.     

Advanced patterning techniques for nanodevice fabrication

The key elements in the fabrication of future devices are lithography and pattern transfer. The continuous advances in miniaturization and increasing integration densities are a direct result of improved lithographic resolution and overlay accuracy. Electron beam direct write and e-beam projection lithography are potential candidates for the mass production of microelectronic devices with critical dimensions below 100 nm. To realize these nanometer patterns by this technology, the performance of exposure tools and resist materials should be increased. In this paper, the method of direct write e-beam lithography is demonstrated and critical issues are discussed.     

Junction fabrication by shadow evaporation without a suspended bridge

We present a novel shadow evaporation technique for the realization of junctions and capacitors. The design by e-beam lithography of strongly asymmetric undercuts on a bilayer resist enables in situ fabrication of junctions and capacitors without the use of the well-known suspended bridge (Dolan 1977 Appl. Phys. Lett. 31 337-9). The absence of bridges increases the mechanical robustness of the resist mask as well as the accessible range of the junction size, from 10(-2) μm(2) to more than 10(4) μm(2). We have fabricated Al/AlO(x)/Al Josephson junctions, phase qubit and capacitors using a 100 kV e-beam writer. Although this high voltage enables a precise control of the undercut, implementation using a conventional 20 kV e-beam is also discussed. The phase qubit coherence times, extracted from spectroscopy resonance width, Rabi and Ramsey oscillation decays and energy relaxation measurements, are longer than the ones obtained in our previous samples realized by standard techniques. These results demonstrate the high quality of the junction obtained by this bridge-free technique.     

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics

Ultrathin crystalline silicon is widely used as an active material for high-performance, flexible, and stretchable electronics, from simple passive and active components to complex integrated circuits, due to its excellent electrical and mechanical properties. However, in contrast to conventional silicon wafer-based devices, ultrathin crystalline silicon-based electronics require an expensive and rather complicated fabrication process. Although silicon-on-insulator (SOI) wafers are commonly used to obtain a single layer of crystalline silicon, they are costly and difficult to process. Therefore, as an alternative to SOI wafers-based thin layers, here, a simple transfer method is proposed for printing ultrathin multiple crystalline silicon sheets with thicknesses between 300 nm to 13 µm and high areal density (>90%) from a single mother wafer. Theoretically, the silicon nano/micro membrane can be generated until the mother wafer is completely consumed. In addition, the electronic applications of silicon membranes are successfully demonstrated through the fabrication of a flexible solar cell and flexible NMOS transistor arrays.     

Direct nanofabrication and transmission electron microscopy on a suite of easy-to-prepare ultrathin film substrates

A high-yield, easy to master method for preparing electron transparent metal, oxide, and carbon ultrathin film substrates suitable for direct nano/micro-fabrication and transmission electron microscopy (TEM) is presented. To demonstrate the versatility of these substrates for fabrication processes, we use e-beam lithography, self-assembled colloidal and protein templates, and microcontact printing to create patterned masks for subsequent electrodeposition of two dimensional and three dimensional structures. The electrodeposited structures range in scale from a few nanometers to a few micrometers in characteristic dimensions. Because fabrication occurs directly on ultrathin films, TEM analysis of the resulting materials and buried interfaces is straightforward without any destructive sample preparation. We show that all the normal TEM analytical methods (imaging, diffraction, electron and X-ray spectroscopies) are compatible with the fabricated structures and the thin film substrates. These electron transparent substrates have largely rendered the need for TEM sample preparation on fabricated structures obsolete in our lab.     

Light Control of Charge Transfer and Excitonic Transitions in a Carbon Nanotube/Porphyrin Hybrid

Carbon nanotube–chromophore hybrids are promising building blocks in order to obtain a controlled electro‐optical transduction effect at the single nano‐object level. In this work, a strong spectral selectivity of the electronic and the phononic response of a chromophore‐coated single nanotube transistor is observed for which standard photogating cannot account. This paper investigates how light irradiation strongly modifies the coupling between molecules and nanotube within the hybrid by means of combined Raman diffusion and electron transport measurements. Moreover, a nonconventional Raman enhancement effect is observed when light irradiation is on the absorption range of the grafted molecule. Finally, this paper shows how the dynamics of single electron tunneling in the device at low temperature is strongly modified by molecular photoexcitation. Both effects will be discussed in terms of photoinduced excitons coupled to electronic levels.     

Two-dimensional photonic crystal resist membrane nanocavity embedding colloidal dot-in-a-rod nanocrystals

A novel technique for the fabrication of photonic crystal (PC) nanocavities coupled with colloidal nanocrystals is presented. A waveguiding resist membrane embedding highly emitting dot-in-a-rod nanocrystals was patterned through e-beam lithography and released through wet etching process. The proposed approach makes the PC structure independent of fabrication imperfections induced by etching steps. Micro-photoluminescence spectra revealed degenerated resonant modes (Q-factor approximately 700) whose fabrication-induced spectral splitting is comparable to the full width at half-maximum of the peaks. Active nanocavities tunable from visible to infrared spectral range on GaAs or Si substrates can be easily implemented by this technique.     

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide

2D semiconductor materials are being considered for next generation electronic device application such as thin‐film transistors and complementary metal–oxide–semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS₂ n‐type transistor and a Si nanomembrane p‐type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition‐metal dichalcogenide materials. The fabricated hetero‐CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air‐stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub‐nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics.     

FT-IR study of a chemically amplified resist for X-ray lithography

Microelectronic devices for future applications demand lithographic performance that falls within the 0.10 microm region and below. Chemically amplified resists (CARs), such as the positive tone commercial UVIII resist, offer a substantial gain in sensitivity, resolution, and process efficiency in deep ultraviolet, e-beam, and X-ray lithographies. In this work, the UVIII resist is characterized for X-ray lithographic applications by studying the "deprotection" or acid generation-diffusion process of the resist under different conditions of post-exposure bake (PEB) temperature and time, and of X-ray exposure dose. The X-ray irradiation from a copper anode at a wavelength of 1.33 nm was at an intensity of 30 microW/cm2 on the resist surface. The deprotection process of the resist during PEB was accurately monitored by using Fourier transform infrared (FT-IR) spectroscopy. The infrared absorption peaks at 1151, 1369, and 2977 cm(-1) in the spectrum of the UVIII resist were found to be useful indicators for the completion of deprotection. Results of the experiments showed that the performance of UVIII could be optimized at the PEB temperature of 140 degrees C, a time of 2 min, and X-ray exposure dose of 12 mJ/cm2. The change in resist thickness after PEB was also measured. The results were confirmed by scanning electron microscopy (SEM) in which a test structure as small as 0.12 microm was obtained in a 1-microm-thick UVIII resist layer.     

电子束在微／纳制造中的应用进展

微纳加工技术推动着集成电路不断缩小器件尺寸和提高集成度,而电子束光刻在纳米光刻技术制作中是最好的方法之一。介绍了近年来电子束光刻技术的研究进展及其在微%纳器件研制中的重要作用。     

Efficient encoding algorithms for computer-aided design of diffractive optical elements by the use of electron-beam fabrication

One of the general requirements of a computer-aided design system is the existence of efficient (in data size and running time) algorithms that are generally reliable for the broadest range of design instances. The restricted data formats of the electron-beam machines impose difficulties in developing algorithms for the design of diffractive optical elements (DOE's) and computer-generated holograms (CGH's). Issues that are related to the development of CGH algorithms for e-beam fabrication of DOE's and CGH's are discussed. We define the problems the CGH algorithms need to solve, then introduce general curve drawing algorithms for the e-beam data generation of diffractive optical components. An efficient algorithm for general aspherical DOE's is proposed. Actual design and fabrication examples are also presented.     

Silicon single electron transistors with SOI and MOSFET structures: the role of access resistances

Coulomb blockade has been widely reported in silicon and metallic structures without intentional tunnel barriers. In particular, a simple constriction in silicon-on-insulator (SOI) allows to build a three-terminal silicon single-electron transistor (SET) operating at moderate temperature. The key parameters are the access resistances confining the electrons and the size of the gate-channel overlap, which sets the Coulomb energy. Thin films of doped silicon with sheet resistance of a few tens of h/e/sup 2/ are well suited for fabricating optimized access resistances. Low doped extensions with typical resistivity 1000 /spl Omega//spl mu/m (at 300 K) are also good candidates. We illustrate this MOS-SET principle in SOI constriction and standard MOSFET of similar size. Although relying on different concepts, the ultimate MOSFET and MOS-SET are shown to be technologically close, differing mostly by the ratio between the channel resistance over the access resistance. Because this ratio is decreasing as the gate length shrinks, single electron effects should become more and more important at high temperature in the subthreshold regime of standard field effect transistor devices.     

A simplified fabrication process of Fresnel zone plates with controlling proximity effect correction

Fresnel zone plates (FZPs) for soft X-ray microscopy with an energy range of 284 eV to 540 eV are designed and fabricated in a simple method. An adequate aspect ratio of the resist mold for electroplating was obtained by the proximity effect correction technology for an incident electron beam on a single thick layer resist. Without additional complicated reactive ion etching, a sufficient electro plating mold for nickel structures was fabricated. The overall fabrication procedures which involve a mix-and-match overlay technique for electron beam lithography and an optic exposure system that centers the membrane on the nanostructures, and hybrid silicon etching technology in junction with deep anisotropy and a KOH wet method in order to release the backside Si substrates of the Si3N4 membranes with no deformation of FZPs are introduced. High quality nanostructures with minimum outermost zone widths of 50 nm and diameters of 120 microm were fabricated with simplified fabrication process and with cost-effective.     

A novel SET/MOSFET hybrid static memory cell design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.