COF结构中键合力损伤芯片Al层的研究

运用实验和有限元模拟相结合的方法，研究了非导电膜和金金共金工艺中键合力对芯片Al压焊块内应力分布的影响，并分析了样品的失效部位和失效原因．挠性基板上印制线宽度不同时键合力对芯片损伤情况的研究表明，小印制线宽度在相同单位面积键合力情况下对Al压焊块损伤较轻．讨论了印制线宽度对键合偏移容差的要求．     

COF结构中键合力损伤芯片Al层的研究

运用实验和有限元模拟相结合的方法,研究了非导电膜和金-金共金工艺中键合力对芯片Al压焊块内应力分布的影响,并分析了样品的失效部位和失效原因.挠性基板上印制线宽度不同时键合力对芯片损伤情况的研究表明,小印制线宽度在相同单位面积键合力情况下对Al压焊块损伤较轻.讨论了印制线宽度对键合偏移容差的要求.     

大型液晶显示用COF带的细节距线路形成

概述了大型液晶显示用COF带的特征和制造技术以及细节距线路形成技术。     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。     

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects     

细间距SMD焊接强度试验研究

通过对细间距SMD焊接强度试验 ,分析了影响焊接强度的诸多因素 ,找到适合SMT要求的焊膏、模板、焊膏量、温度曲线等系列工艺材料参数。     

密脚间距QFP集成电路引线成形工艺研究

集成电路引线成形原本是集成电路封装的后道工序,成形质量将直接影响电子装联产品的可靠性,其关键工艺点在于成形的肩宽、站高、焊接长度和共面度等关键工艺参数的选择以及成形工艺装备的合理配置与优化.论述了目前表面贴装密脚间距QFP封装器件在应用中遇到的引线成形问题,介绍了该类器件成形中的相关技术要求及目前国内外器件成形的现状,提出了引线手工成形的解决方案.     

精细挠性印制板

介绍了精细化FPC的制造工艺及其最新技术的研究。     

细间距器件焊点桥接研究

根据能量最小原理建立SMT焊点形态预测的三维数学模型,模拟了焊点桥接成形过程并对模拟结果进行实验验证。通过分析模拟结果,对SMT焊点钎料桥接机理进行理论研究。     

Electrodeposition of Indium Bumps for Ultrafine Pitch Interconnection

Electroplating is a promising method to produce ultrafine pitch indium bumps for assembly of pixel detectors in imaging applications. In this work, the process of indium bumping through electrodeposition was demonstrated and the influences of various current waveforms on the bump morphology, microstructure and height uniformity were investigated. Electron microscopy was used to study the microstructure of electroplated indium bumps and a Zygo white light interferometer was utilised to evaluate the height uniformity. The results indicated that the bump uniformities on wafer, pattern and feature scales were improved by using unipolar pulse and bipolar pulse reverse current waveforms.     

Fine‐Pitch Solder on Pad Process for Microbump Interconnection

A cost‐effective and simple solder on pad (SoP) process is proposed for a fine‐pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60‐μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine‐pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine‐pitch SoP process and evaluate the fine‐pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45‐μm diameter and 60‐μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine‐pitch SoP and microbump interconnection using a screen printing process.     

精细间距SMT模板的制作研究

本文介绍了表面贴装技术以及模板的工艺技术要求,论述了采用光刻技术制造SMT模板的工艺过程。解决模板制造工艺中底片双面精确贴装、蚀刻体系及精度要求等关键技术。