一种用于加速FPGA设计空间探索的电路特性驱动半监督建模方法

该文提出一种电路特性驱动的半监督建模方法来探索FPGA架构设计空间。通过加入电路特性作为输入来构建一个通用的FPGA性能模型,该方法能够精确预测指定电路在特定FPGA架构上实现的性能。实验结果显示该方法在预测电路在FPGA上实现的面积时,平均相对误差达到6.25%;预测延时时,平均相对误差可达4.23%,具有与半监督模型树(Semi-supervised Model Tree, SMT)方法可比的预测精度。同时,该文方法加速了FPGA性能建模过程,与SMT方法比较,在6核Intel服务器平台Intel Xeon E7-4807上,探索具有百万架构的FPGA设计空间时,该文方法可将时间成本由500 h降低为250 h。     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法,它综合了top-down和bottom-up两种时钟树拓扑产生方法,以最小时钟延时和总线长为目标,并把合理偏差应用到时钟树的构造中.电路测试结果证明,与零偏差算法比较,该算法有效地减小了时钟树的总体线长,并且优化了时钟树的性能.     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法 ,它综合了 top- down和 bottom- up两种时钟树拓扑产生方法 ,以最小时钟延时和总线长为目标 ,并把合理偏差应用到时钟树的构造中 .电路测试结果证明 ,与零偏差算法比较 ,该算法有效地减小了时钟树的总体线长 ,并且优化了时钟树的性能     

基于与非锥的新型FPGA逻辑簇互连结构研究

该文针对新型FPGA可编程逻辑单元与非锥(And-Inverter Cone, AIC)的结构特性,提出一系列方案以得到优化的逻辑簇互连结构,包括:移除输出级交叉矩阵,单级反相交叉矩阵,低负载电路优化,将反馈和输出选择功能分开,限制AIC输出级数的基础上移除中间级交叉矩阵,与LUT架构进行混合等。通过大量的实验,得出针对面积延时积最优的AIC簇互连结构,与Altera公司的FPGA芯片Stratix-IV结构相比,该结构逻辑功能簇本身面积减小9.06%, MCNC应用电路集在基于优化的AIC FPGA架构上实现的平均面积延时积减小40.82%, VTR应用电路集平均面积延时积减小17.38%;与原有的AIC结构相比,簇面积减小23.16%, MCNC应用电路集平均面积延时减小27.15%, VTR应用电路集平均面积延时积减小15.26%。     

基于PSO算法的FPRM电路延时和面积优化

RM(Reed-Muller)电路的极性决定其延时和面积,通过对粒子群优化(Particle Swarm Optimization,PSO)算法和FPRM表达式的研究,提出较大规模FPRM电路延时和面积优化算法.首先根据FPRM表达式特点,建立延时和面积估计模型;然后结合PSO算法和极性转换算法,对FPRM电路进行最佳延时和面积极性搜索;最后对PLA格式MCNC Benchmark电路进行测试,结果表明:与穷尽算法相比,PSO算法效率更高;与基于遗传算法的FPRM电路优化结果相比,延时平均节省6.6%,面积平均减少11.1%.     

传感器网络中基于最短路径树的低延时节能路由算法

借助图论中最短路径和最小生成树的原理,在无线传感器网络中构建若干棵以Sink节点为根的最短路径源路由树。与最小生成树相比,最短路径树能保证路径上大部分节点找到节点间RSSI较强的通讯路径并以较少的跳数把数据传输给Sink节点,而最小生成树中的节点则需较多跳数。因此,提出的算法在一定程度上降低了延时。算法通过事先设定最低RSSI和节点最大剩余能量MRE来构建路由树,并修改已存在的路由算法,从而保证节点通讯的可靠性和网络的节能。     

基于超像素分割和混合权值AdaBoost运动检测算法

针对长时间目标跟踪检测不准确问题,提出一种结合运动场景的超像素分割与混合权值的Ada Boost多目标检测(ABSP)算法。首先在动态模型中,计算Ada Boost算法的混合权值,检测运动目标,确定搜索区域,提高多目标跟踪检测能力;在训练阶段,采用SLIC分割与Mean-Shift聚类形成超像素图块,构建目标外观模型;在跟踪阶段,结合超像素特征池生成模板直方图与置信图,构建观测模型与运动模型,采用粒子滤波与贝叶斯模型,计算最大后验估计,实现遮挡运动目标检测。结果表明:能够有效处理数目变化多目标检测与遮挡问题,提高了检测的实时性。     

基于深度学习的智能电网窃电检测混合模型研究

针对传统窃电检测模型受维度诅咒、类不平衡等问题,提出一种能有效检测智能电网窃电行为的混合深度学习模型,利用深度学习卷积神经网络（AlexNet）处理维度诅咒问题,显著提升数据处理的准确性;通过自适应增强（Ada Boost）对正常和异常用电行为分类,进一步提高分类精度;使用欠采样技术解决类不平衡问题,确保模型在各类数据的均衡性能;利用人工蜂群算法对AdaBoost和AlexNet的超参数进行优化,有效提高整体模型性能。使用真实智能电表数据集评估混合模型的有效性,与同类模型相比,提出的混合深度学习模型在准确率、精确度、召回率、F1分数、马修斯相关系数（MCC）和曲线下面积-接收者操作特征曲线（AUC-ROC）分数上分别达到了88%、86%、84%、85%、78%和91%,不仅提高了用电行为监测的准确性,也为电力系统的智能分析提供了新视角。     

基于多策略离散粒子群算法的MPRM电路延时与面积优化

针对大规模混合极性Reed-Muller(Mixed Polarity Reed-Muller,MPRM)逻辑电路的延时与面积优化,提出一种基于多策略离散粒子群优化(Multi-Strategy Discrete Particle Swarm Optimization,MSDPSO)的极性搜索方法.在MSDPSO算法中,对粒子进行团队划分,每个团队既执行不同策略,又相互联系,并行完成探索与开发的双重任务.同时在进化过程中采用高斯调整来激活寻优能力较差的粒子.结合MSDPSO算法和列表极性转换技术,对大规模MPRM电路进行延时与面积极性搜索.最后对PLA格式的MCNC Benchmark电路进行算法性能测试,结果验证了MSDPSO算法的有效性.与离散粒子群优化(Discrete Particle Swarm Optimization,DPSO)算法的优化结果相比较,MSDPSO算法获取的电路延时平均缩短8.43%,面积平均节省38.36%.     

降低泄漏电流的细粒度休眠晶体管插入法

首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.     

Optimized superpixel and AdaBoost classifier for human thermal face recognition

Infrared spectrum-based human recognition systems offer straightforward and robust solutions for achieving an excellent performance in uncontrolled illumination. In this paper, a human thermal face recognition model is proposed. The model consists of four main steps. Firstly, the grey wolf optimization algorithm is used to find optimal superpixel parameters of the quick-shift segmentation method. Then, segmentation-based fractal texture analysis algorithm is used for extracting features and the rough set-based methods are used to select the most discriminative features. Finally, the AdaBoost classifier is employed for the classification process. For evaluating our proposed approach, thermal images from the Terravic Facial infrared dataset were used. The experimental results showed that the proposed approach achieved (1) reasonable segmentation results for the indoor and outdoor thermal images, (2) accuracy of the segmented images better than the non-segmented ones, and (3) the entropy-based feature selection method obtained the best classification accuracy. Generally, the classification accuracy of the proposed model reached to 99% which is better than some of the related work with around 5%.     

一种基于与非锥簇架构FPGA输入交叉互连设计优化方法

该文针对与非锥(And-Inverter Cone, AIC)簇架构FPGA开发中面临的簇面积过大的瓶颈问题,对其输入交叉互连设计优化进行深入研究,在评估优化流程层次,首次创新性提出装箱网表统计法对AIC簇输入和反馈资源占用情况进行分析,为设计及优化输入交叉互连结构提供指导,以更高效获得优化参数。针对输入交叉互连模块,在结构参数设计层次,首次提出将引脚输入和输出反馈连通率分离独立设计,并通过大量的实验,获得最优连通率组合。在电路设计实现层次,有效利用AIC逻辑锥电路结构特点,首次提出双相输入交叉互连电路实现。相比于已有的AIC簇结构,通过该文提出的优化方法所得的AIC簇自身面积可减小21.21%,面积制约问题得到了明显改善。在实现MCNC和VTR应用电路集时,与Altera公司的FPGA芯片Stratix IV(LUT架构)相比,采用具有该文所设计的输入交叉互连结构的AIC架构FPGA,平均面积延时积分别减小了48.49%和26.29%;与传统AIC架构FPGA相比,平均面积延时积分别减小了28.48%和28.37%,显著提升了FPGA的整体性能。     

A high performance hardware architecture for portable,low-power retinal vessel segmentation

The retina of the human eye and more particularly the retinal blood vasculature can be used in several medical and biometric applications. The use of retinal images in such applications however, is computationally intensive, due to the high complexity of the algorithms used to extract the vessels from the retina. In addition, the emergence of portable biometric authentication applications, as well as onsite biomedical diagnostics raises the need for real-time, power-efficient implementations of such algorithms that can also satisfy the performance and accuracy requirements of portable systems that use retinal images. In an attempt to meet those requirements, this work presents a VLSI implementation of a retina vessel segmentation system while exploring various parameters that affect the power consumption, the accuracy and performance of the system. The proposed design implements an unsupervised vessel segmentation algorithm which utilizes matched filtering with signed integers to enhance the difference between the blood vessels and the rest of the retina. The design accelerates the process of obtaining a binary map of the vessels tree by using parallel processing and efficient resource sharing, achieving real-time performance. The design has been verified on a commercial FPGA platform and exhibits significant performance improvements (up to 90×) when compared to other existing hardware and software implementations, with an overall accuracy of 92.4%. Furthermore, the low power consumption of the proposed VLSI implementation enables the proposed architecture to be used in portable systems, as it achieves an efficient balance between performance, power consumption and accuracy.     

4.2 Gbit/s single-chip FPGA implementation of AES algorithm

A high performance encryptor/decryptor core of the advanced encryption standard (AES) is presented. The proposed architecture is implemented on a single-chip FPGA using a fully pipelined approach. The results obtained show that this design offers up to 25.06% less area and yields up to 27.23% higher throughput than the fastest AES FPGA implementations reported to date.     

A better technique using multisegment modeling and analysis of high-density and high-speed connectors

A useful and rather new simulation technique for connectors up to 6.25 GHz is presented and discussed in this paper. The proposed model extracts electrical parameters of a connector using time-domain reflectometry (TDR) measurements. A new technique was developed to obtain accurate impedance profiles using TDR and a multisegment approach that is effectively a distributed coupled model. The parameter extraction and characterization of connectors are discussed. The performance of the proposed segmented transmission line model is verified by simulation of the model in SPICE and by experimental measurement. The results show that the proposed model can simulate the electrical characteristics, including crosstalk and impedance, of high-density and high-speed connectors with satisfactory accuracy. Based on the proposed modeling and CAD simulators, the design and analysis of complicated high-density and high-speed connectors can be executed accurately and effectively. Compared with other previous models, the proposed model can significantly improve the accuracy of simulation.     

Real-Time Implementation of Parallel Architecture Based Noise Minimization from Speech Signals on FPGA

In recent years, the real time hardware implementation of LMS based adaptive noise cancellation on FPGA is becoming popular. There are several works reported in this area in the literature. However, NLMS based implementation of adaptive noise cancellation on FPGA using Xilinx System Generator (XSG) is not reported. This paper explores the various forms of parallel architecture based on NLMS algorithm and its hardware implementation on FPGA using XSG for noise minimization from speech signals. In total, the direct form, binary tree direct form and transposed form of parallel architecture of normalized least mean square (NLMS), delayed normalized least mean square and retimed delayed normalized least mean square algorithms are implemented on FPGA using hardware co-simulation model. The performance parameters (SNR and MSE) of these algorithms are analyzed for the adaptive noise cancellation system and the comparison is made with parallel architectures of least mean square (LMS), delayed least mean square, and retimed delayed least mean square algorithms respectively. The hardware utilization of all the said algorithms are also analyzed and compared. The result shows that NLMS based implementations outperform than that of LMS for all forms of parallel architecture for the given parameters with negligence increase in device utility. The binary tree direct form of retimed delayed NLMS achieves the maximum SNR improvement (39.83 dB) in comparison to other NLMS variants at the cost of optimum resource utilization.     

基于半监督学习的SVM-Wishart极化SAR图像分类方法

该文针对极化SAR (Synthetic Aperture Radar)图像分类中的小样本问题,提出了一种新的半监督分类算法。考虑到极化SAR数据反映了地物的散射特性,该方法首先利用目标分解方法提取了多种极化散射特征;其次,在协同训练框架下结合SVM分类器构建了协同半监督模型,该模型可以同时利用有标记和无标记样本对极化SAR图像进行分类,从而在小样本时可以获得更好的分类精度;最后,为进一步改善分类结果,在协同训练分类完成后,该方法又利用Wishart分类器对分类结果进行修正。理论分析与实验表明,该算法在只有少量标记样本的情况下优于传统算法。