A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of \(0.08\,\hbox {mm}^2\) . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is \(76\,\upmu \hbox {W}\) from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.     

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using \(0.18\,\upmu \hbox {m}\) CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of \(-6\)  dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of \(-60, -110, -52\) and \(-64\)  dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.     

A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell

Recently introduced MOS-FGMOS split length cell has been used to increase the DC gain of a fully differential op amp. Resultant proposed opamp structure exhibits gain of 97 dB and unity gain bandwidth of 400 MHz with power consumption of 1.2 mW. An opamp design has been verified with Cadence Spectre using a 130 nm technology at 1.2 V and has a slew rate of \(53\,\hbox {V}/\mu \hbox {s}\) with a phase margin of \(78^{\circ }\) .     

Low Voltage Low Cost Quadrature Oscillator Based on Active Inductor

This paper presents a new low voltage low cost quadrature oscillator, which consists of two LC negative oscillators based on active inductor. In this quadrature oscillator, the back-gates of the core transistors are used as coupling terminals to provide the quadrature outputs. The proposed floating active inductor has a two layer transistor structure. The quadrature oscillator has been implemented with the chart 0.18  \(\upmu \) m CMOS technology. At the supply voltage of 1.2 V, the total power consumption is 16 mW. The phase noise at 1 MHz frequency offset is \(-\) 111.8 dBc/Hz at the oscillation frequency of 3.946 Hz.     

Soft X-ray Absorption and Photoemission Spectroscopy Study of Cobalt-Based Thermoelectric Oxides: \hbox{Ca}_3\hbox{Co}_4\hbox{O}_9, \hbox{Ca}_3\hbox{Co}_2\hbox{O}_6, and \hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}

The electronic structures of Co-based potential thermoelectric (TE) oxides, including $\hbox{Ca}_3\hbox{Co}_4\hbox{O}_9$ and $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ (y = 8 + δ) single crystals and polycrystalline $\hbox{Ca}_3\hbox{Co}_2\hbox{O}_6$ , have been investigated by employing soft x-ray absorption spectroscopy (XAS) and photoemission spectroscopy (PES). Co 2p XAS measurements show that Co ions are nearly trivalent ( $\hbox{Co}^{3+}$ ) in all of these Co-based TE oxides with a small mixture of $\hbox{Co}^{4+}$ ions in $\hbox{Bi}_{2}\hbox{Sr}_{2}\hbox{Co}_2\hbox{O}_{y}$ . Valence-band PES and O 1s XAS measurements show that the occupied Co 3d states are located at the top of the valence bands and that the lowest unoccupied states have the primarily Co 3d character, respectively. These findings suggest the importance of the Co 3d electronic structures in determining TE properties of these Co-based oxides.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications

This paper describes a 0.8 V 700 μW CMOS low-voltage regulated cascode trans-impedance amplifier (TIA). It reduces the need for extra bias voltages compared to other recent low-voltage regulated cascode topologies. A trans-impedance gain of around 60 dBΩ along with a 40 GHz bandwidth was achieved using the 0.13 μm IBM CMOS process technology. The input referred noise current spectral density was below $ {{{18{\mathrm{pA}}}} \left/ {{\sqrt {\mathrm{Hz}} }} \right.} $ within the -3 dB noise bandwidth. Eye diagram simulations using a ?53dBm input photo-diode current signal and a 2³¹-1 pseudo random bit sequence data pattern, indicates an eye opening of 90 % at 10Gbit/s and 50 % at 40Gbit/s. This proposed RGC TIA is thus a robust building block for numerous optical sensing applications with low bit error ratio (BER) figure.     

Demonstration of using multi-band 16-QAM OFDM modulation with direct-detection in 10 GHz bandwidth for 37.3-Gb/s PON

We propose and experimentally demonstrate a 37.3 Gb/s passive optical network using four-band orthogonal-frequency-division-multiplexing (OFDM) channels within 10 GHz bandwidth. Here, the required sampling rate and resolution of digital-to-analog/analog-to-digital (DA/AD) converter are only 5 GS/s and 8 bits to accomplish the 40 Gb/s OFDM downstream rate. Moreover, to reduce the power fading and fiber chromatic dispersion issues, a $-$ 0.7 chirp parameter Mach-Zehnder modulator is used for the four-band OFDM modulation scheme. Downstream negative power penalty of $-$ 0.37 dB can be obtained at the bit error rate of $3.8\times 10^{-3}$ after 20 km standard single mode fiber transmission without dispersion compensation.     

Theory and design of a CT \Updelta\Upsigma modulator with low sensitivity to loop-delay variations

This paper presents a 3rd-order, 3-bit continuous-time (CT) $\Updelta\Upsigma$ Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm². It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.     

A broadband, differential transimpedance amplifier in 0.35 μm SiGe BICMOS technology for 10 Gbit/s fiber optical front-ends

This study focuses on 10 Gbit/s differential transimpedance amplifier. At the beginning of the work, the amplifier circuit is deeply analyzed and is optimized for the best phase linearity over the bandwidth resulted in a group delay variation less than 1 ps. The amplifier circuit is designed with 0.35 μm SiGe heterojunction bipolar transistor BICMOS process. 9 GHz bandwidth, almost 58 dBΩ transimpedance gain with less than 11.18 pA/ $ \sqrt {\text{Hz}} $ averaged input-referred noise current are achieved. Electrical sensitivity is 15 μA_pp. Power consumption is 71 mW at 3.3 V single power supply.     

Performance Analysis of Microwave Radio Refractivity on Radio Field Strength and Radio Horizon Distance Over Akure,Nigeria

Surface radio refractivity studies are being carried out in Akure, \((7.15^{\circ }\hbox {N}, 5.12^{\circ }\hbox {E})\) South-Western Nigeria, by in-situ measurement of atmospheric pressure, temperature, and relative humidity using Wireless Weather Station (Integrated Sensor Suit, ISS). Five years of measurement (January, 2007–December, 2011) were used to compute the surface radio refractivity and its diurnal, daily, seasonal and yearly variations are analyzed. The results were then used to compute radio horizon distance \((\hbox {R}_\mathrm{DH})\) and examine the field strength (FSV) variability. Results obtained show that the surface radio refractivity, \(\hbox {N}_\mathrm{s}\) , varies with the time of the day as well as the seasons of the year. High values of \(\hbox {N}_\mathrm{s}\) were recorded in the morning and evening hours while the values were minima around 1,500 h local time. An average value of surface radio refractivity of 364.74 N-units was obtained for this location. The annual maximum mean of FSV is 15.24 dB and the minimum is 2.20 dB. This implies that the output of a receiving antenna in Akure may generally be subject to variations not less than 2 dB in a year, but can be as high as 15 dB.     

Design and modeling of high-resolution multibit log-domain \Delta \Sigma modulators

Log-domain Delta-Sigma ( $\Delta \Sigma$ ) modulators are attractive for implementing analog-to-digital (A/D) converters (ADCs) targeting low-power low-voltage applications. Previously reported log-domain $\Delta \Sigma$ modulators were limited to 1-bit quantization and, hence, could not benefit from the advantages associated with multibit quantization (namely, reduced in-band quantization noise, and increased modulator stability). Unlike classical $\Delta \Sigma$ modulators, directly extending a log-domain $\Delta \Sigma$ modulator with a 1-bit quantizer to a log-domain $\Delta \Sigma$ modulator with a multibit quantizer is challenging, in terms of CMOS circuit implementation. Additionally, the realization of log-domain $\Delta \Sigma$ modulators targeting high-resolution applications necessitates minimization of distortion and noise in the log-domain loop-filter. This paper discusses the challenges of multibit quantization and digital-to-analog (D/A) conversion in the log-domain, and presents a novel multibit log-domain $\Delta \Sigma$ modulator, practical for CMOS implementation. SIMULINK models of log-domain $\Delta \Sigma$ modulator circuits are proposed, and the effects of various circuit non-idealities are investigated, including the effects of log-domain compression–expansion mismatch. Furthermore, this paper proposes novel low-distortion log-domain analog blocks suitable for high-resolution analog-to-digital (A/D) conversion applications. Circuit simulation results of a proposed third-order 3-bit class AB log-domain $\Delta \Sigma$ loop-filter demonstrate 10.4-bit signal-to-noise-and-distortion-ratio (SNDR) over a 10 kHz bandwidth with a $0.84\,V_{pp}$ differential signal input, while operating from a 0.8 V supply and consuming a total power of $35.5\,\upmu \hbox {W}.$      

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.