An analytical approach for physical modeling of hot-carrier induced degradation

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.     

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

Towards understanding recovery of hot-carrier induced degradation

This article treats the recovery of hot-carrier degraded nMOSFETs by annealing in a nitrogen ambient. The recovery rate is investigated as a function of the annealing temperature, where the recovery for increasing temperatures is in agreement with the passivation processes. At the original post-metal anneal temperature of T = 400 °C, the device's original performance is fully restored. Higher temperatures induce a permanent, unrecoverable change to the devices, manifested in a gradual V_T shift. The recovery rate is found to be independent of both the transistor gate length and the cooling rate (quench, slow and stepped cooling) upon annealing. These findings are used to gain further understanding of the mechanisms behind the recovery of hot-carrier damage. The recovery rate exhibits Arrhenius behavior and the recovery data are consistent with Stesmans' recovery model.     

Temperature dependence of the channel hot-carrier degradation ofn-channel MOSFET's

The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I_d-V_g characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping     

On the channel-length dependence of the hot-carrier degradation ofn-channel MOSFETs

The channel-length dependence of lifetime plots is analyzed. It is shown that no unique τ*I_d versus I_sub/I_d relation can be obtained when threshold-voltage shifts are used for measuring the lifetime. In contrast, when using charge pumping as a monitor for the degradation, the lifetime plot for a given technology proves to be independent of the channel length     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

Suppression of hot-carrier degradation in Si MOSFETs by germaniumdoping

Presently there are two approaches to the reduction of hot-carrier effects in Si MOSFETs: the use of lightly-doped-drain/double-diffused-drain (LDD/DDD) structures and the reduction of applied bias. Both of these suffer certain penalties. A technique for incorporating Ge impurities in the channel that creates additional scattering so that `lucky' hot carriers are less probable is introduced. Results indicate that while the initial MOSFET characteristics are maintained, the degradation rate under voltage stress is much reduced     

Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs

The influence of parasitic charge at the Si–SiO₂ interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25?nm is studied. The results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunnelling current.     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

A reassessment of ac hot-carrier degradation in deep-submicrometer LDD N-MOSFET

In deep submicrometer N-MOSFET, a "backdrop" of substantial defect generation by the quasi-static V/sub g/=V/sub d/ stress phase is shown to significantly influence the accuracy of interpretation of ac stress data. If neglected, a severe overestimation of ac stress induced degradation would result. Through an approach that eliminates this damage component from the overall ac stress damage, increased parametric shifts, associated with the gate pulse transition phase, are found to occur in different time windows, delineated by the relative importance of hot-hole and hot-electron induced damage at different stages of the stress, the interaction between the two damages at specific stages of the stress, as well as the sensitivities of the device parameters to the spatial evolution of the two damages.     

Simulation of hot-carrier induced MOS circuit degradation for VLSIreliability analysis

A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates     

Modelling of hot-carrier degradation and its application for analog design for reliability

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.     

The impact of NMOSFET hot-carrier degradation on CMOS analogsubcircuit performance

This study presents some of the first experimental data on the impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance. Because of circuit design requirements, most NMOSFET's used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, in addition to interface states, significant numbers of hole traps are also generated inside the gate oxide. Because acceptor-type interface states are mostly unoccupied in the saturation region, hole traps are found to have a much more significant impact on analog NMOSFET device performance. The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are examined     

A new insight into the degradation behavior of the LDD N-MOSFETduring dynamic hot-carrier stressing

A new degradation behavior of LDD N-MOSFETs during dynamic hot-carrier stress is presented. Increased degradation occurs during the gate pulse transition, and involves hot-hole injection that initially begins in the oxide-spacer region, and later propagates to the channel region. Experimental results clearly show that increased degradation of the linear drain current and transconductance is mainly due to hole-induced interface traps in the oxide-spacer region. Electron trapping at hole-induced oxide defects, on the other hand, is mainly responsible for the enhanced threshold voltage shift in the late stage, when hole injection coincides with electron injection in the channel region     

Precise quantitative evaluation of the hot-carrier induced drain series resistance degradation in LATID-n-MOSFETs

A method is presented which allows to distinguish the drain series resistance increase from other mechanisms contributing to the drain current degradation of hot-carrier stressed n-MOSFETs. Devices with different channel lengths but equal damages are used. The different degradation mechanisms are characterized quantitatively and a model for the drain current degradation is presented. For short stress times, the drain current degradation is dominated by series resistance degradation. For long stress times, however, the contribution of the mechanisms attributed to an “equivalent channel length increase” prevails.     

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.     

A physical-based analytical model for hot-carrier inducedsaturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits