A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

A possible mechanism for reconciling large gate-drain overlapcapacitance with a small difference between polysilicon gate length andeffective channel length in an advanced technology PFET

A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO₂ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,     

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler-Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.     

Fairness in wireless microcellular networks

In the design of cellular and microcellular telecommunication networks, it is common to consider service to subscribers in specific regions by more than a single base station. Although the service overlap provides certain advantages, such as performance improvement achieved in dynamic channel assignment, it results in a large variance in the quality of service across the cells. In this paper, we introduce channel restriction to achieve fairness in the network quality of service. We develop analytical and simulation models for network performance and examine the advantages gained in increased system throughput and reduced probability of handover failure. The numerical results indicate that restricting the number of available channels to users in the overlap region results in considerable improvement in the carried traffic and mean probability of blocking. Finally, we discuss the possibility of substituting or scaling down the guard channels with channel restriction to achieve the desired effect of reduced forced termination     

A surface potential-based compact model of n-MOSFET gate-tunneling current

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling. This work presents a novel physics-based compact model of gate current in the n-MOSFET. A simplified version of the Esaki-Tsu formula is developed to calculate the tunneling current density, in which the original integral is approximated to retain the essential physics without sacrificing computational efficiency required in a compact model. The proposed model is surface potential-based in both the channel and source/drain overlap regions. The channel component of the gate current is physically partitioned into the source and drain parts using a symmetrically linearized version of the charge-sheet model. The partition is implemented in analytical form and accounts for the drain bias dependence of the channel component. A small number of adjustable parameters is sufficient to reproduce the experimentally observed bias and geometry dependence of the gate current for several advanced processes.     

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation

The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p-channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm²/V-sec are deduced for drain voltages ranging from ?1·2 V to ?7 V. This compares to channel hole mobility values of 200–300 cm²/V-sec at room temperature. It is found that the channel width is on the order of 30–50 Å—appreciably less than that at room temperature.     

A DC and small signal AC model for organic thin film transistors including contact effects and non quasi static regime

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices.The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation.The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Observation of oxide breakdown and its effects on thecharacteristics of ultra-thin-oxide nMOSFET's

Ultra-thin gate oxide breakdown in nMOSFET's has been studied for an oxide thickness of 1.5 nm using constant voltage stressing. The pre- and post-oxide breakdown characteristics of the device have been compared, and the results have shown a strong dependence on the breakdown locations. The oxide breakdown near the source/drain-to-gate overlap regions was found to be more severe on the post-breakdown characteristics of the device than breakdown in the channel. This observation may be related to the dependence of breakdown on the distribution of electric field and areas of different regions within the nMOSFET under stress     

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.     

Trap effects in p-channel GaAs MESFET's

After processing of conventional n-channel GaAs MESFETs, traps in the channel and channel interface regions cause several deleterious parasitic device effects. It is known that a p-well GaAs MESFET structure eliminates all of the undesirable parasitic effects in n-channel devices; moreover, complementary p-channel MESFETs are realizable with the same p-well technology. The hole capture and emission processes of deep-level traps associated with p-channel GaAs MESFETs are characterized here using temperature-dependent drain current transient measurements. The transient behavior is dominated by trapping in the channel-substrate interface region analogous to an n-channel MESFET. By employing a one-level model to extract the activation energy and capture cross section, the traps in the channel-substrate region of the p-channel MESFET are attributed to an EL2 antisite defect (As_Ga )     

NBTI degradation in STI-based LDMOSFETs

NBTI degradation in STI-based LDMOSFETs has been investigated by multi-region DCIV spectroscopy (MR-DCIV), a non-destructive and sensitive method to probe the interface states on channel, accumulation and STI region. A unified MR-DCIV current model was proposed based on its independency to the forward bias and temperature. Under the same negative gate stress condition, MR-DCIV current degradation was compared for nLDMOSFET and pLDMOSFET. Much larger MR-DCIV current shift was observed at channel and accumulation region with thin gate oxide thickness, indicating interface states generation at related regions. Our results show that more significant degradation for multi-finger device was consistent with NBTI degradation mechanism. High voltage device design with thermal management consideration is of crucial importance to guaranteeing the device performance and reliability.     

Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET) measured by gated-diode configuration

In this paper the hot carrier degradation behavior of the SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET’s) is investigated based on the forward gated-diode configuration. With peak diode current as an indicator, the hot carrier induced degradation of SOI n-DTMOSFET’s is compared with the corresponding SOI nMOSFET’s. Due to the connection of the gate and the body and thus the positive-biased source–body and drain–body junction, the SOI n-DTMOSFET’s exhibit lower peak diode current than the conventional counterparts, showing smaller generated defect density and thus lower hot carrier induced degradation. The generated defect distribution in SOI n-DTMOSFET is analyzed. It is shown that despite of the tied gate-body, the peak of the generated defect density tends to lie in the gate-to-drain overlap region. The defect distribution exerts different influences on the diode current of the long channel device and short channel device with different electric field. Moreover, even with the positive biased body, the generated defects in SOI DTMOSFT are more apt to flow to front interface rather than back interface, resulting in the more severe degradation of the front interface in SOI n-DTMOSFET’s. This gives the main flow direction of the generated defects.     

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.     

Degradation mechanism understanding of NLDEMOS SOI in RF applications

The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation.     

基于模型拟合的重叠信号盲分离方法

本文提出一种多信号分离方法.方法利用多项式相位拟合估计信号相位,构建了多信号分离模型,从而把多信号分离转化为序列和信道参数估计问题,然后利用序列和信道参数估计的方法进行多个信号的幅度和相位的联合估计.利用估计得到的序列和信道参数恢复多个信号各自的相位和幅度,从而对多个信号进行分离.该方法只需利用单个信道接收,并能够对完全重叠的多个信号进行分离.仿真和实际实验证明了方法的优异性能.     

Analytical charge control model for AlGaN/GaN MIS-HFETs including an undepleted barrier layer

An analytical charge control model considering the insulator/AlGaN interface charge and undepleted Al-GaN barrier layer is presented for AlGaN/GaN metal-insulator-semiconductor heterostructure field effect transistors (MIS-HFETs) over the entire operation range of gate voltage. The whole process of charge control is analyzed in detail and partitioned into four regions: Ⅰ-full depletion, Ⅱ-partial depletion, Ⅲ-neutral region and Ⅳ-electron accu-mulation at the insulator/AlGaN interface. The results show that two-dimensional electron gas (2DEG) saturates at the boundary of region Ⅱ/Ⅲ and the gate voltage should not exceed the 2DEG saturation voltage in order to keep the channel in control. In addition, the span of region Ⅱaccounts for about 50% of the range of gate voltage before 2DEG saturates. The good agreement of the calculated transfer characteristic with the measured data confirms the validity of the proposed model.     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances