Decoded-source sense amplifier for high-density DRAMs

The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V_cc of 4 V at 85°C     

Threshold difference compensated sense amplifier

A dynamic flip-flop sense amplifier compensating for threshold difference between a pair of transistors by way of offset storage technique is presented. The DC and AC analyses on input offset voltage and performance limitations are discussed. Experimental results have shown that input offset is less than 2 mV with a 5 V single power supply, over a wide temperature range and a wide common mode input voltage range.     

一种应用于EEPROM读出放大器的设计

读出放大器是电可擦除非易失性存储器(EEPROM)中的关键模块,其读取速度决定了EEPROM的操作频率。基于国内先进的0.18μm工艺,对EEPROM放大器的基准电流源和比较器进行了分别设计,测试结果显示读出放大器的响应时间小于70 ns,可满足10 MHz的EEPROM存取速度的要求。     

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃.     

622MHz current-mode sense amplifier

A current-mode sense amplifier, operating at 622 MHz, in a 0.8 μm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing     

Thermal management for high-power active amplifier arrays

Much of the active array work reported to date has been directed toward the demonstration of prototypes at low-power levels. Analysis results presented here show that overheating failures will occur as these arrays are scaled to reasonable output powers. Large air-cooled heat sinks attached to the backside of a thinned array can be used for single-sided designs such as oscillator arrays, but heat sinking becomes substantially more difficult for two-sided transmission-type arrays. For these designs, a possible solution is described which uses an aluminum-nitride dielectric layer to facilitate conduction to heat sinks on the array's perimeter     

Characterization of an MOS sense amplifier

A novel technique to characterize MOS sense amplifiers is described. The technique does not perturb the operation of the sense amplifier during characterization. An MOS sense amplifier has been characterized using this technique for various power supply and clock conditions. The characterization results are given to demonstrate the sensitivity of the technique.     

A novel high-speed sense amplifier for Bi-NOR flash memories

A novel high-speed current-mode sense amplifier is proposed for Bi-NOR flash memory designs. Program and erasure of the Bi-NOR technologies employ bi-directional channel FN tunneling with localized shallow P-well structures to realize the high-reliability, high-speed, and low-power operation. The proposed sensing circuit with advanced cross-coupled structure by connecting the gates of clamping transistors to the cross-coupled nodes provides excellent immunity against mismatch compared with the other sense amplifiers. Furthermore, the sensing times for various current differences and bitline capacitances and resistances are all superior to the others. The agreement between simulation and measurement indicates the sensing speed reaches 2ns for the threshold voltage difference of lower than 1 V at 1.8-V supply voltage even with the high threshold voltage of the peripheral CMOS transistors up to 0.8 V.     

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash(eFlash)memory applications.The topology of the sense amplifier is based on current mode comparison.Moreover,an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current.The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process,and the sense time is 0.43 ns at 1.5 V,corresponding to a46% improvement over the conventional technologies.     

一种适应于高性能嵌入式闪存的低压灵敏放大器

本文提出了一种适应于高性能嵌入式闪存的低压灵敏放大器,通过采用电流比较技术和自动消失调技术,该灵敏放大器在低电源电压下获得了很好的性能,改善了低电流阈值窗口存储器的读取速度。基于上海宏力半导体制造公司130nm的嵌入式闪存工艺,该灵敏放大器的感应时间在1.5V的电源电压下达到了0.43ns,其感应速度比传统的灵敏放大器提高了46%     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented,based on a very simple direct current-mode comparison.It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage,low power and high precision.The proposed amplifier can sense a 0.5μA current gap and work with a lowest voltage of 1V.In addition,the current power of a single amplifier is optimized by 15%.     

一种适应于flash memory的超低压和高速的感应放大器设计

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct current-mode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 μ A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.     

Quasistatic analysis of a dynamic sense amplifier

Quasistatic analysis of a dynamic sense amplifier has been carried out to analyse the initial conditions. As a result of the analysis we obtain a relationship between the hold time and the storage capacitance and also the minimum storage capacitance required to facilitate proper latching for a fixed threshold voltage difference between the latching transistors.     

A high-performance very low-voltage current sense amplifier for nonvolatile memories

A high-performance sense amplifier for nonvolatile memories capable of working under a very low-voltage power supply is presented. The topology of the sense amplifier uses a pure current-mode comparison allowing power supplies lower than 1 V to be used and includes two subcircuits which improve slew rate performance. The sense amplifier was implemented in an EEPROM realized with a 0.18-/spl mu/m EEPROM technology. Experimental results showed a read access time of about 30 ns with a power supply of 1.65 V.     

步入商用的MRAM技术

存储芯片被广泛应用在计算机、手机、音乐播放器、数码相机、家电设备、飞机和汽车上,已经达到了几平无所不在的程度。不过,不同的存储产品具有不同的优点和缺点,使得它们的应用各自受到局限。一般来说,每一个电子设备都会使用好几种存储芯片,以弥补各自的不足。例如静态随机存取存储芯片（SRAM）或随机存取存储芯片（DRAM）被广泛用于计算机等设备,它们具有非常快的存取速度,但在掉电的情况下会丢失全部数据。闪存芯片（FLASH）则常见于音乐播放器、数码相机或是手机,它们可以在掉电时也保存数据,不过存取速度相对比较慢,同时随着时间推移,数据会丢失。     

High-speed charge transfer sense amplifier for 0.5 V DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.     

用两个电流检测放大器解决一个放大器的限制

新一代汽车和工业设计在精确控制和诊断功能以及可靠性和安全功能方面面临着越来越高的要求.实现这些新功能常常需要精确的电流检测,因此近年来对精确的高压侧电流检测放大器的需求出现了稳步增长.高压侧电流检测放大器用途很广,可以用在电动机伺服控制、螺线管定位、电池充电和放电电路以及过流监视器和短路故障检测器等各种应用中.     

A high performance sense amplifier for a 5 V dynamic RAM

Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing by conventional techniques, and is used in the Fairchild 64K design. Design requirements and a detailed analysis of the amplifier are presented along with simulated results, followed by performance data. The circuit analysis shows how the key design parameters should be chosen and the effects of clock timing variations on the performance of the sense amplifier.