共查询到20条相似文献，搜索用时 15 毫秒
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基于FPGA的CSD编码乘法器 总被引：1，自引：1，他引：1
在数字滤波、离散傅里叶变换等数字信号处理中,乘法运算是一个最基本的运算,乘法运算的速度决定着数字系统的运算速度。本文通过理论与实验研究相结合的方法介绍CSD编码乘法器的运算法则及其在FPGA中的实现过程。通过与二进制乘法器相比较,证明CSD编码乘法器在减少对FPGA资源的占用和提高运算速度方面具有明显的效果。 相似文献
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Thirumalesu Kudithi Sakthivel R 《International Journal of Circuit Theory and Applications》2020,48(8):1256-1273
Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs. 相似文献
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Limin Yu Shen Xu Huaxin Zhang Longxing Shi Weifeng Sun 《International Journal of Circuit Theory and Applications》2021,49(1):114-127
High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution. 相似文献
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输电线路关键部件的检测对电力系统的设备安全及系统稳定运行起着关键作用.基于机器视觉和深度学习的输电塔线巡检技术检测耗能大,花费时间长,难以满足高效低耗与实时检测的要求.为了完成对输电线路部的快速准确识别,本文将生物视觉理论中特征提取计算模型和更为高效的脉冲神经网络相结合,提出了一种基于脑启发的多层神经元网络模型以模拟视... 相似文献
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为获取TS5643N100型绝对式编码器的位置和状态信息,提出采用现场可编程逻辑器件(Field Pro-grammable Gate Array,FPGA)编程实现TS5643N100型绝对式编码器的解码电路,并将这些信息作为反馈信号输入伺服控制器.该FPGA解码电路采用模块化设计,其主要包括对编码器输出信号的解码、串并转换、CRC校验和数据分离处理等.实验结果表明,所设计的FPGA解码电路能够实现TS5643N100型绝对式编码器和后续处理器之间的通讯,便于上位机控制器读取编码器采集的信息,可以替代价格昂贵的AU5688专用转换芯片,进而简化系统结构设计,降低产品成本. 相似文献
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《International Journal of Circuit Theory and Applications》2017,45(11):1497-1513
T he main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first‐order and second‐order all‐pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round‐off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan‐6 and Virtex‐6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd. 相似文献
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基于DSP+FPGA技术的实时视频采集系统的设计 总被引：11，自引：0，他引：11
本文介绍了一种基于高速数字信号处理器TMS320DM642和FPGA的图像采集系统,阐述了该系统的硬件组成、工作原理,并详细描述了视频编码单元、图像处理单元和视频输出单元等的构成和设计方法,分析了系统设计时的各个关键技术环节.本系统有3个突出的优点:一是实时性,硬件电路器件的执行速度以及适合硬件的软件系统都保证了系统实时性的实现:二是小型化、集成度高,这个系统功能由一块PCB板实现:三是系统硬件平台的通用型,可以通过软件编程实现各种不同的图像处理功能. 相似文献
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针对高阶幅度相移键控(amplitude phase shift keying, APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array, FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10-5的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。 相似文献
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Guo Chun Wan Wen Jing Liu Ying Qian Zhang Mei Song Tong 《International Journal of Numerical Modelling》2019,32(1)
This paper proposes an efficient modeling of series‐parallel structure for the digital downconversion (DDC) implemented in the field programmable gate array for astronomical observation system. The received signals by a radio telescope are of intermediate frequency, and they can be stored and analyzed only after having been converted into digital baseband signals. Although many algorithms have been proposed for the traditional DDC, it is still hard to balance the working frequency of signals and the hardware resources of field programmable gate array. The proposed series‐parallel structure can not only solve the problem but also provide a more compact size, lower consumption of power, and transplanting ability for the DDC module. The new structure has been used for the signal processing of pulsars in an astronomical observation system, and those merits have been validated. 相似文献
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Ramji Gupta Alpana Pandey Rajendra Kumar Baghel 《International Journal of Numerical Modelling》2019,32(5)
A true random number generator (TRNG) is a basic building block of many modern cryptographic systems. As field programmable gate array (FPGA) has a flexible architecture and low‐cost test cycle, hence, it becomes an ideal platform for hardware implementation of digital systems. This paper presents an FPGA implementation of a high‐speed TRNG that is based on a chaotic oscillator at 100 MHz frequency with speed of 1600 Mbps. The experimental results show that the proposed generator is faster and more compact than the existing chaotic ring‐oscillator‐based TRNGs, and further, it is verified that the generated bit sequences pass all TRNG tests in National Institute of Standards and Technology (NIST SP 800‐22). The proposed TRNG is implemented in two FPGA families: Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3 XC7A35T1CPG236C (Artix 7) Xilinx Vivado v.2017.3 design suite. 相似文献