An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs.     

基于FPGA的CSD编码乘法器

在数字滤波、离散傅里叶变换等数字信号处理中,乘法运算是一个最基本的运算,乘法运算的速度决定着数字系统的运算速度。本文通过理论与实验研究相结合的方法介绍CSD编码乘法器的运算法则及其在FPGA中的实现过程。通过与二进制乘法器相比较,证明CSD编码乘法器在减少对FPGA资源的占用和提高运算速度方面具有明显的效果。     

FPGA‐based implementation for improved control scheme of grid‐connected PV system with 3‐phase 3‐level NPC‐VSI

The large scale penetration of renewable energy resources has boosted the need of using improved control technique and modular power electronic converter structures for efficient and reliable operation of grid‐connected systems. This study investigates the performance of a grid‐connected 3‐phase 3‐level neutral‐point clamped voltage source inverter for renewable energy integration by using improved current control technique. For medium or high‐voltage grid interfacing, the multilevel inverter structure is generally used to reduce the voltage stress across the switching device as well as the harmonic distortion. The neutral‐point clamped voltage source inverter is controlled by using decoupling technique along with the proper grid synchronization via moving average filter–based phase‐locked loop. The moving average filter–based phase‐locked loop is used to reduce the delay in grid angle estimation under balanced as well as distorted grid conditions. A Lyapunov‐based approach for analysing the stability of the system has also been discussed. In this study, the hardware‐in‐loop (HIL) simulation of the control algorithm and the grid synchronization technique is realized using Virtex‐6 FPGA ML605 evaluation kit. The performance of the system is analyzed by conducting a time‐domain simulation in the Matlab/Simulink platform and its performance is examined in the HIL environment. The simulation and the hardware cosimulation results are presented to validate the effectiveness of the proposed control scheme.     

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.     

A fast acoustic field mapping approach based on fabry–perot sensor with high‐speed camera

A Fabry–Perot (FP) interferometer‐based ultrasound sensor provides an inherently broadband response and excellent detection sensitivity compared to piezoelectric zirconate titanate (PZT) or polyvinylidene difluoride (PVDF) transducers. It is therefore expected to be used for medical ultrasound imaging and photoacoustic imaging. However, at present, mapping acoustic fields takes much time for scanning, which hinders real‐time measurement. We propose a new approach that utilizes a high‐speed camera (HSC) to map acoustic fields without mechanical scanning and to sample signals of acoustic waves with the shutter of the HSC. Experimental results indicate that acoustic field at the focus of a pulsed 1‐MHz PZT ultrasound transducer can be detected and mapped by using the FP sensor with the HSC. By improving the uniformity of the FP sensor and the exposure time, the frame rate of HSC can be further developed, and this approach should be able to provide a fast acoustic field mapping for high‐resolution biomedical photoacoustic and other ultrasonic imaging. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.