A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

基于时间放大技术的时间数字转换器的设计

本文基于时间放大技术设计了一种两步式的时间数字转换器(TDC),可应用于高精度的飞行测量领域。本设计采用SMIC 55 nm CMOS工艺,采用环形延时TDC作为粗量化电路,采用游标式TDC作为细量化电路。游标式TDC的精度受到延时失配限制,导致在设计时难以突破更高精度的要求。时间放大器通过放大粗量化产生的时间余量,并继续进行第二次细量化,降低了细量化电路的设计难度。针对传统时间放大器输入范围有限以及放大精确度不足的弊端,提出一种新的时间放大器结构,具有精确放大宽范围输入时间间隔的能力。仿真结果表明,采用该种时间放大器的TDC可实现的分辨率为3.7 ps,测量范围为80 ns,微分非线性(DNL)为0.73 LSB,积分非线性(INL)为0.95 LSB,该设计能够在高线性度下更好地兼顾TDC的分辨率与测量范围。     

A Technique of Automatically Tuning Decision Parameters for Rule‐Based Defect Classifier

In automatic defect classification of semiconductor wafers using scanning electron microscope images, we propose a technique of tuning decision parameters for rule‐based defect classifiers. The proposed method adopts a coarse‐to‐fine search for reduction in processing time. However, due to search leakage, there is no guarantee that the same solutions as in a full parameter search can be obtained. In order to prevent leakage in the coarse search theoretically, the proposed method evaluates a candidate parameter set based on the estimated range of classification accuracy attained by not only the candidate but the surrounding solutions eliminated by the coarse search. Experiments on real image data demonstrate the effectiveness of the proposed method. The proposed method can extract the same solutions as the full parameter search within almost the same processing time as the conventional coarse‐to‐fine search. When the sampling step of the coarse search is three to six, while the tuning time of the conventional coarse‐to‐fine search is 1 to 21 s, that of the proposed method is 5 to 35 s.     

GRO‐TDC with gate‐switch‐based delay cell halving resolution limit

In this paper, we propose a time‐to‐digital converter (TDC) with first‐order noise‐shaping. The proposed gated ring oscillator (GRO)‐TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate‐switched configuration to solve the charge redistribution problem. The proposed GRO‐TDC is designed using a 65‐nm process technology, with an area of 0.015 mm² and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO‐TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO‐TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

Method of Shortening Settling Time Using Final State Control for High‐Precision Stage with Decouplable Structure of Fine and Coarse Parts

High‐precision stages require high‐speed and high‐precision control to improve their production throughput and quality. However, their motion speed and accuracy are expected to reach a limit in the near future if the conventional high‐precision stage structure is used. Therefore, the authors designed and fabricated a “catapult stage,” which has a structure that can be decoupled into a fine stage and coarse stage. The catapult stage is different from conventional dual stages in which the fine stage is disturbed by the coarse stage because they contact each other. This paper proposes a novel control system design for the catapult stage and a control method that shortens the settling time by using final state control (FSC). So far, FSC has mainly been used for applications such as hard disk drives, for which the initial states are zero. However, it is important to consider the initial states for the catapult stage because the initial position, velocity, and acceleration of the catapult stage are not equal to zero. Simulations and experiments were performed to demonstrate the effectiveness of the proposed methods.     

Delay‐locked loop based clock and data recovery with wide operating range and low jitter in a 65‐nm CMOS process

A delay‐locked loop (DLL) based clock and data recovery (CDR) circuit with a half‐rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process using a 1.2‐V supply voltage. The simulation results show that it can cover a wide operating range from 500 Mbps to 8 Gbps and the corresponding peak‐to‐peak jitters are 1.63 ps and 0.96 ps, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Robust design of CMOS amplifiers oriented to settling‐time specification

In this paper, we propose a new approach for the robust design of complementary metal‐oxide‐semiconductor amplifiers based on settling‐time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling‐time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two‐stage amplifier and a three‐stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright © 2016 John Wiley & Sons, Ltd.     

Bessel‐like compensation of three‐stage operational transconductance amplifiers

In this paper, we introduce a simple and well‐defined approach for the design of fast settling amplifiers suitable for switched‐capacitor circuits and characterized by low capacitive loads, in the order of few pico‐farad. In the specific, the design is based on a new Bessel‐like compensation that sets the phase of the closed‐loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The proposed Bessel‐like approach is validated through the design and the simulation of two 3‐stage amplifiers in a 65‐nm CMOS process.     

An improved two‐stage image registration algorithm for super‐resolution

This paper presents an improved two‐stage image registration algorithm for super‐resolution. The algorithm is based on the rotation–translation (RT) model and the coarse‐to‐fine strategy. It first uses the phase correlation algorithm to estimate large‐scale displacements with pixel‐level accuracy after image motion compensation, and then uses the Keren algorithm to obtain high‐accuracy sub‐pixel estimation. Moreover, from the non‐commutative property between rotation and translation in the RT model, synthesis formulae are derived and used to combine the two results together, which could further improve the accuracy without extra computational costs. The algorithm can achieve high‐accuracy sub‐pixel registration for large‐scale displacements, which also has the advantage of good computational efficiency. To illustrate the effectiveness of the algorithm, both simulations and practical super‐resolution reconstruction experiments are performed. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Variation‐aware widely tunable nanoscale design of CMOS active inductor‐based RF bandpass filter

This paper presents a novel design methodology for realizing a variation‐aware widely tunable active inductor‐based RF bandpass filter (BPF). The inductor‐less filter is designed and implemented using voltage differencing transconductance amplifier (VDTA) as an active building block and a grounded capacitor, thereby validating its suitability for fully integrated circuit applications. Digital ‘coarse’ tuning and analog ‘fine’ tuning are employed to achieve better frequency coverage. The designed filter exhibits a tuning range of 1.65–3.015 GHz and a 3‐dB bandwidth of 1400–122 MHz which translates into a quality factor of 1.17–24.71. It offers a voltage gain of 0–22.91 dB, noise figure of 28.16–28.95 dB, has a 1‐dB compression point of 2.50–2.478 dBm and draws 0.065–0.232 mW power from 1‐V power supply. Our proposed design shows a figure‐of‐merit of 82.08–91.27 dB, which is higher as compared to its counterparts available in the literature. The filter is implemented in 45‐nm CMOS technology node using metal gate and strained silicon. Copyright © 2017 John Wiley & Sons, Ltd.     

Multistage multiphase switched‐capacitor DC–DC converter with variable‐phase and PWM control

A closed‐loop multistage multiphase switched‐capacitor converter (n‐stage p‐phase MPSC) is proposed with a variable‐phase control (VPC) and a pulse‐width‐modulation (PWM) technique for low‐power step‐up conversion and high‐efficiency regulation. In this n‐stage MPSC, n voltage doublers are connected in series for boosting the voltage gain up to 2ⁿ at most. Here, VPC is suggested to realize a variable multiphase operation by changing the phase number p and topological path for the more suitable level of voltage gain so as to improve the power efficiency, especially for the lower output voltage Besides, PWM is adopted not only to enhance output regulation for different desired outputs, but also to reinforce output robustness to source/loading variation. Further, some theoretical analyses and designs include: n‐stage p‐phase MPSC model, steady‐state analysis, conversion ratio, power efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed‐loop MPSC is simulated, and the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Output‐feedback model‐reference adaptive calibration for map‐based anti‐jerk control of electromechanical automotive clutches

It is well known that the map‐based control can reduce the computational burden of the automotive on‐board controller. This paper proposes an output‐feedback model‐reference adaptive control algorithm to calibrate the map‐based anti‐jerk controller for electromechanical clutch engagement. The algorithm can be used to adaptively construct a data‐driven fuzzy rule base without resorting to manual tuning, so that it can overcome the problem of conventional knowledge‐based fuzzy logic design, which involves strenuous parameter‐tuning work in the construction of calibration maps. To accurately define the consequent of each fuzzy rule for anti‐jerk control, an output feedback law for computing the reference trajectory of clutch engagement is developed to eliminate the discontinuous slip‐stick transition, whereas an adaptive controller is designed to track the reference trajectory and compensate the nonlinearity. The convergence of the proposed output‐feedback model‐reference adaptive control algorithm is analyzed. Simulation results indicate that the proposed method can successfully reduce the excessive vehicle jerk and frictional energy dissipation during clutch engagement as compared with the conventional knowledge‐based fuzzy logic controller without fine tuning.     

A large dynamic‐range,high dB‐linearity VGA using switch arrays and second‐order mismatch‐shaping DEM technique

A new large dynamic‐range variable gain amplifier (VGA) with improved dB linearity is presented. The traditional cascade VGA has the disadvantages of gain mismatch between sub‐stages and difficulty of employing mismatch cancelation or suppression algorithms. In this paper, switch arrays were used to make the sub‐stages or called gain cells in the coarse‐tuning stage (CTS) work independently and therefore prevent the integral operation of the gain errors. Then, a second‐order mismatch‐shaping DEM was applied conveniently to the CTS and shown to be a useful design technique in improving the dB‐linearity performance. The cascade VGA and its second‐order mismatch‐shaping DEM had been integrated in a 2.4‐GHz receiver chip which was fabricated in a 0.18‐µm CMOS technology with a supply voltage of 1.8 V. Measurement results showed that the gain errors were significantly reduced with second‐order mismatch‐shaping DEM with respect to the traditionally thermometric decoding over a temperature range of [?40, 80] °C. Copyright © 2015 John Wiley & Sons, Ltd.     

Improving Networks‐on‐Chip performability: A topology‐based approach

The performability metric is commonly used in Networks‐on‐Chip (NoC)‐based systems to represent their abilities to successfully complete specific tasks in finite time intervals. In this paper, we present a novel topology‐based performability model for NoC‐based systems. The model is used to evaluate the performability of NoC‐based systems at early design phases. A comparative study of nine commonly used network architectures is performed using the proposed model. The purpose of the study is to explore the impact of the network topology on the performability of NoC‐based systems. Using the output from this study, a new methodology is proposed to improve the performability of a given application at early design phases. In this methodology, a joint consideration of five design parameters (network topology, target application traffic distribution, mapping of processing elements, noise power, and voltage swing) is carried out. Using the proposed methodology, designers can select the optimal topology for a given application that maximizes system performability. The effectiveness of the proposed methodology in determining the optimal topology is verified by experimental work and validated through a case study of a video application. Copyright © 2010 John Wiley & Sons, Ltd.     

A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents

A new leakage‐tolerant true single‐phase clock dual‐modulus prescaler based on a stage‐merged scheme is presented. Leakage‐restricting transistors are used to reduce the leakage currents at critical nodes, and leakage‐related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40‐nm process shows that the proposed divide‐by‐2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs. Copyright © 2016 John Wiley & Sons, Ltd.