A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R² is 0.99 and verify the effect of duty cycle compensation.     

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

Neutralizing interferences in two‐hop amplify‐and‐forward MIMO relay systems

In this paper, we present the interference neutralization technique for two‐hop multiple‐input multiple‐output (MIMO) relay systems. It enables multiple MIMO transmitters (sources) to simultaneously transmit independent data streams to their MIMO receivers (destinations) without mutual interferences, thereby improving spectral efficiency of the systems. To neutralize the mutual interferences using multiple amplify‐and‐forward (AF) MIMO relays, we establish the sufficient condition for the antenna configuration in the MIMO relay networks, and provide a filter design technique for the AF MIMO relays. The proposed method increases sum rates of the systems linearly with the number of transmitters participating in simultaneous transmission. To improve the sum rates further, this method is combined with transmit power allocation using the water‐filling algorithm. In addition, it is shown that by employing the minimum number of relays required to meet the sufficient condition, the system cost for the proposed method can be reduced without compromising the sum rate performance severely. Finally, simulation results successfully demonstrate that by exploiting radio resources such as frequency and time efficiently, the proposed method achieves a higher sum rate than the existing techniques based on interference avoidance. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel electrode‐area‐weighted method of implementing wavelet transform processor with surface acoustic wave device

The objective of this research was to investigate the possibility of a novel electrode‐area‐weighted (EAW) method of implementing wavelet transform processor (WTP) with surface acoustic wave (SAW) device. The motivation for this work was prompted by a diffraction problem of the WTP using SAW device. In this paper, we propose a novel EAW method in order to solve the diffraction problem. When the electrode areas of the EAW wavelet interdigital transducer (IDT) (i.e. the input IDT) are designed according to the envelope areas of the wavelet function, the impulse‐response function of the EAW wavelet IDT is equal to the wavelet function, so that the novel EAW WTP using SAW device can be fabricated. In this study, we also present the diffraction problem, the substrate material, and the electrode number of the output IDT as three key problems, and the solutions to the three key problems are implemented. Copyright © 2016 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

Visualization of high‐speed phenomena using an acousto‐optic laser deflector

An acousto‐optic laser deflector was used for visualization of high‐speed phenomena, such as shock waves and density perturbations accompanying an impulse discharge, or shock waves generated by laser‐induced breakdown in air. Using a continuous wave laser as the light source, shadowgraphs of shock waves and density perturbations were obtained at shutter speeds down to 1µs. Results showed that shock waves propagated at a speed of 417 m/s in the case of an impulse discharge, and 485 m/s in the case of laser‐induced breakdown. Prebreakdown phenomena such as leaders progressing from the high‐voltage electrode were also visualized. Compared to conventional high‐speed imaging techniques, this method is useful when using a laser light source, since the acousto‐optic crystal can accommodate high‐intensity laser light. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 154(3): 9–15, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20279     

Design and analysis of low‐speed,high‐torque permanent magnet motors

This paper presents design and analysis of low‐speed, high‐torque permanent magnet motors. The motor has 16‐pole, 18‐coil construction, and a unique winding arrangement to produce high torque. The simplified torque analysis is proposed considering the line of magnetic induction distribution in the motor. The validity of the proposed analysis has been proved by both linear and nonlinear FEM analyses. The 500‐Nm, 200‐rpm test motor has been designed and constructed and the motor shows the expected characteristics. © 2000 Scripta Technica, Electr Eng Jpn, 132(3): 48–56, 2000     

Rejection of unknown periodic disturbances for continuous‐time MIMO systems with dynamic uncertainties

Rejection of unknown periodic disturbances in multi‐channel systems has several industrial applications that include aerospace, consumer electronics, and many other industries. This paper presents a design and analysis of an output‐feedback robust adaptive controller for multi‐input multi‐output continuous‐time systems in the presence of modeling errors and broadband output noise. The trade‐off between robust stability and performance improvement as well as practical design considerations for performance improvements are presented. It is demonstrated that proper shaping of the open‐loop plant singular values as well as over‐parameterizing the controller parametric model can significantly improve performance. Numerical simulations are performed to demonstrate the effectiveness of the proposed scheme. Copyright © 2016 John Wiley & Sons, Ltd.     

Optimum design approach for low‐speed,high‐torque permanent magnet motors

This paper presents an optimum design approach for low‐speed, high‐torque permanent magnet motors. The approach is divided into two steps: the first consists of the rough estimation of torque by linear analysis, and the second the optimization of the motor configuration by nonlinear FEM analysis. Under restricted dimensional specifications and electrical requirements, a 16‐pole, 18‐coil permanent magnet motor with a rating of 600 Nm and 300 rpm was designed and constructed. © 2001 Scripta Technica, Electr Eng Jpn, 135(4): 52–63, 2001     

Adaptive control design for MIMO switched nonlinear systems with full state constraints

This paper presents an adaptive fuzzy control approach of multiple‐input–multiple‐output (MIMO) switched uncertain systems, which involve time‐varying full state constraints (TFSCs) and unknown disturbances. In the design procedure, the fuzzy logic systems are adopted to approximate the unknown functions in the systems. The adaptive fuzzy controller is set up by backstepping technique. According to the tangent barrier Lyapunov function (BLF‐Tan), a novel adaptive MIMO switched nonlinear control algorithm is designed. Under the rule of arbitrary switchings and the proposed control laws, it is demonstrated that all signals in the resulted system are semiglobally uniformly ultimately bounded (SGUUB) and the tracking error converges to a small neighborhood of zero with TFSCs. Furthermore, the simulation example validates the effectiveness of presented control strategy.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

High‐speed and high‐precision position control using a sliding mode compensator

To achieve high‐speed, high‐precision position control for semiconductor product machines and industrial robots, full‐closed feedback control is applied. Many control methods have been proposed for such a system. In general, proportional position control and proportional plus integral velocity control or integral plus proportional velocity control (P,PI/I‐P), which is a type of proportional plus integral plus differential control (PID), is applied in many industrial applications. However, in the case of changing mechanical characteristics of the control target, the parameters of P,PI/I‐PI control must also change in order to maintain good motion performance. In this paper, we propose a new P,PI/I‐P control method that includes a nonlinear compensator. The algorithm of the nonlinear compensator is based on sliding mode control with chattering compensation. The effectiveness of the proposed control method is evaluated using a full‐closed single‐axis slider system via point‐to‐point control and contour control in the case of changing load. The experimental results indicate that the proposed control method is robust in the case of changing acceleration/deceleration of control reference, changing load, and low‐velocity contour motion. © 2010 Wiley Periodicals, Inc. Electr Eng Jpn, 174(2): 65–71, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21011     

Development of a high‐speed laser interferometer using an acousto‐optic deflector

An acousto‐optic laser deflector was used as a shutter for high‐speed imaging of laser interference fringes using an ordinary CCD camera. The exposure duration was set by the pulse width of the high‐frequency signal applied to the acousto‐optic deflector. Changes in laser interference fringes due to an impulse discharge in air were obtained at an exposure duration of 4 µs. By applying a sequence of high‐frequency signals with different frequency, the beam was deflected to four different angles at different times, allowing four interference images to be captured on a single video frame. This was used for time‐resolved imaging of the interference fringe pattern. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 148(2): 76–83, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20011     

Modeling of noise and distortion associated with ultra‐high‐speed modulation of VCSEL with slow‐light feedback

This paper presents numerical modeling on the noise properties and signal distortion associated with millimeter‐frequency modulation of vertical‐cavity surface‐emitting laser (VCSEL) under with a transverse‐coupled cavity. The study is based on a time‐delay rate equation model that takes into account the multiple round trips in the feedback cavity and the optical loss and phase delay in each round trip. Strong slow‐light feedback is found to boost the modulation bandwidth to frequencies approaching 70 GHz and induce resonance modulation due to photon–photon resonance (PPR) over passbands centered on frequencies reaching 90 GHz. We show that the relative intensity noise of the VCSEL with resonance modulation is enhanced when the noise frequency approaches the corresponding PPR frequency VCSEL. The same effect applies for the VCSEL with extended carrier‐photon resonance (CPR) at the CPR frequency. The low‐frequency part is characterized by flat (white) noise of level nearly equal to −140 dB/Hz. The second‐harmonic distortion (2HD) values are smaller than −10 dB under small‐signal modulation and increase to lower than −5 dB when the modulation index becomes 0.3. Copyright © 2015 John Wiley & Sons, Ltd.     

Series resonant ZCS‐PFM DC‐DC power converter with high‐frequency high‐voltage transformer link for high‐power magnetron drive

This paper presents a single lossless inductive snubber‐assisted ZCS‐PFM series resonant DC‐DC power converter with a high‐frequency high‐voltage transformer link for industrial‐use high‐power magnetron drive. The current flowing through the active power switches rises gradually at a turned‐on transient state with the aid of a single lossless snubber inductor, and ZCS turn‐on commutation based on overlapping current can be achieved via the wide range pulse frequency modulation control scheme. The high‐frequency high‐voltage transformer primary side resonant current always becomes continuous operation mode, by electromagnetic loose coupling design of the high‐frequency high‐voltage transformer and the magnetizing inductance of the high‐frequency high‐voltage transformer. As a result, this high‐voltage power converter circuit for the magnetron can achieve a complete zero current soft switching under the condition of broad width gate voltage signals. Furthermore, this high‐voltage DC‐DC power converter circuit can regulate the output power from zero to full over audible frequency range via the two resonant frequency circuit design. Its operating performances are evaluated and discussed on the basis of the power loss analysis simulation and the experimental results from a practical point of view. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 153(3): 79–87, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20126     

An indirect adaptive pole‐placement control for MIMO discrete‐time stochastic systems

In this paper, an indirect adaptive pole‐placement control scheme for multi‐input multi‐output (MIMO) discrete‐time stochastic systems is developed. This control scheme combines a recursive least squares (RLS) estimation algorithm with pole‐placement control design to produce a control law with self‐tuning capability. A parametric model with a priori prediction outputs is adopted for modelling the controlled system. Then, a RLS estimation algorithm which applies the a posteriori prediction errors is employed to identify the parameters of the model. It is shown that the implementation of the estimation algorithm including a time‐varying inverse logarithm step size mechanism has an almost sure convergence. Further, an equivalent stochastic closed‐loop system is used here for constructing near supermartingales, allowing that the proposed control scheme facilitates the establishment of the adaptive pole‐placement control and prevents the closed‐loop control system from occurring unstable pole‐zero cancellation. An analysis is provided that this control scheme guarantees parameter estimation convergence and system stability in the mean squares sense almost surely. Simulation studies are also presented to validate the theoretical findings. Copyright © 2005 John Wiley & Sons, Ltd.