Noise generation,propagation and effects on RF components in system-on-a-chip packaging

Substrate coupling noise effects in wireless receiver systems in terms of the crosstalk power spectral density induced from the fast switching digital circuits is the center of study in this paper. Deterioration in performance of a low noise amplifier is plotted against various values of die-attach inductance, inductance on digital ground pins, physical separation between the analog and digital circuits on-chip, number of simultaneous switching output buffers, etc. Different Ball Grid Array Packages, both the wire bonded and flip-chip attached versions have been studied. The return loss and insertion loss for paths from the on-chip wire bond pad to connect pads on the printed circuit boards have been plotted. Results show that noise reduces by a greater amount for reduction in die-attach inductance as compared to a reduction in inductance on the digital ground pin.     

PCB设计中同步开关噪声问题分析

印刷电路板设计中的同步开关噪声问题是现代高速数字电路应用的瓶颈之一。介绍了一 种在电路板上施加同步开关报文和温度应力的可靠性测试方法,该方法可以有效暴露电路 板上的同步开关噪声问题。借助噪声测试和阻抗分析手段,对一个由该方法发现的异常问 题进行了分析,通过优化去耦电容和电源平面阻抗,抑制了电路板上的同步开关噪声, 问题得到了完美解决。最后,给出了一些在PCB设计中抑制同步开关噪声的方法和建议。     

Switching noise picked up by a planar dipole antenna mounted nearintegrated circuits

For applications in which antennas are located near or in integrated circuits (ICs), the switching noise from digital circuits can interfere with the operation of antennas. This paper presents a study of the switching noise picked up by a planar dipole antenna from a divide-by-128 IC located near the antenna. To develop understanding of the measurement results, a lumped-element simulation model has been developed. Quantitative agreements between the measurements and simulations for numerous experiments have been obtained. The measurements indicate that by selecting the signal frequency on the antennas much greater than the circuit frequency, the immunity from switching noise can be improved. The measurements also showed that circuits such as buffers are relatively noisier, and emanate more noise at higher operating frequencies. Finally, the measurements showed that using antennas with a differential or balanced feed structure can substantially reduce the coupling of switching noise (~20 dB) which is mostly common-mode in nature     

On integrated circuit bidirectional amplifiers

Describes the development of two bidirectional digital amplifiers for use in cellular switching structures and cellular computers. An evaluation of several circuits resulted in the development of two new and different circuits, which meet the previously mentioned requirements. The circuits have been evaluated by computer simulation and one of the circuits was constructed on an integrated circuit chip to prove its practicality. The resulting circuits are different from all other bidirectional digital amplifiers. They require no clock signals for operation and noise does not cause them to latch up. This represents a significant advance in the design of bidirectional digital amplifiers and makes possible their use in areas in which they were previously considered impractical.     

一种抑制SSN的新型宽带平面电磁带隙结构

随着现代高速数字电路的快速发展,同步开关噪声(SSN)问题变得越来越突出。该文提出了一种适用于高速数字电路中抑制同步开关噪声的新型宽带平面电磁带隙(EBG)结构,并用Ansoft HFSS软件对该电磁带隙结构进行数据仿真分析。仿真结果表明,在抑制深度为-30dB时,其阻带范围为0.2~5.6 GHz,与传统的L-bridge型电磁带隙结构比较,阻带下限截止频率下降了500 MHz,阻带带宽增加了1.4GHz,相对带宽增加了38.1%,且能全向抑制同步开关噪声。     

On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips

This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share.In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.     

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control voltages on the loop filter to be immune to the channel-length modulation. Due to the digital nature, the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency synthesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110 dBc/Hz at an offset frequency of 1 MHz.     

SWAN: high-level simulation methodology for digital substrate noise generation

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.     

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a$hboxp^+ $/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18$muhbox m$3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring.     

Behavioral EMI models of complex digital VLSI circuits

Increasing EMI potential of high-performance digital circuits like 32bit microcontrollers demand for switching current models and feasible ways to run netlist-based EMI simulations. A promising modeling approach for digital VLSI circuits is presented and a silicon test vehicle for correlation between models and measurements is described.     

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-/spl mu/m CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design.     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

数字化功率因数补偿器的设计

数字化功率因数补偿器与一般的无功功率补偿装置不同．它由一片可擦除只读存储器芯片ＥＰＲＯＭ２７６４及组合逻辑电路等组成，可及时读出当时的功率因数和需补偿的电容数据，从而完成数字显示和补偿电容的切换控制．该方法成本低，控制精度高，抗干扰性能好．文章介绍了具体电路的设计、显示与切换的分时执行方式以及数据编制与电容的选择等．     

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead     

Substrate-aware mixed-signal macrocell placement in WRIGHT

We describe a set of placement algorithms for handling substrate coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed-signal placement optimization     

Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.     

指导nM0S数字电路元件级设计的开关信号理论

本文指出了布尔代数在指导数字电路设计中的不足,并在区分描写开关状态与信号的二类变量的基础上建立了能反映数字电路内开关元件与信号相互作用过程的开关信号理论。本文把该理论具体用于对nMOs数字电路的研究,结果表明该理论可很好地指导nMOS数字电路在元件级的逻辑设计。     

Ultra-high speed modulation-doped field-effect transistors: atutorial review

A tutorial review on the modulation-doped field-effect transistor (MODFET) and its application to ultra-low-noise, medium-power, and ultra-wide-band traveling-wave amplifiers as well as ultra-high-speed digital logic circuits is presented. It is believed that with further advances in material growth and device scaling significant improvements in cutoff frequencies, switching speed, noise, and power will be achieved in the near future