Characterization of human metal ESD reference discharge event and correlation of generator parameters to failure levels-part II: correlation of generator parameters to failure levels

Most electrostatic discharge (ESD) generators are built in accordance with the IEC 61000-4-2 specifications. It is shown, that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprised of fast CMOS devices, while rise time and derivative of the discharge current did not correlate well. The electric parameters of typical ESD generators and ESD generators that have been modified to reflect the current and field parameters of the human metal reference event are compared and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of the first paper, of this two-paper series, are discussed with respect to reproducibility and test severity.     

基于状态方程法的不同ESD电路对比分析

针对IEC 61000-4-2中规定的典型静电放电(electrostatic discharge, ESD)电流波形存在拟合多样性且不易通过具体电路实现这一问题, 采用求解电路状态方程组的方法对四种ESD模拟器电路进行了计算.得到了四种指数形式的ESD电流解析表达式, 绘制了相应的电流曲线, 分别讨论了四种ESD模拟器电路产生的ESD电流波形解析式的连续性和可导性, 并对不同电路产生的ESD电流波形与IEC 61000-4-2标准规定电流波形之间的差异进行了对比分析.结果表明不同ESD电路产生的电流波形的四个主要指标符合IEC 61000-4-2标准规定, 但由于电路的拓扑结构和元件参数不同, 求得的电流波形解析式的连续性和可导性存在差异, 因此在选择ESD模型时, 应根据实际的人体参数和放电枪参数确定合适的电路结构.该计算方法适用于求解集总参数电路, 为ESD电磁脉冲辐射场仿真计算提供了新的电流解析式.     

ESD reliability and protection schemes in SOI CMOS output buffers

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<>     

New substrate-triggered ESD protection structures in a 0.18-μm CMOS process without extra mask

In order to quickly discharge the electrostatic discharge (ESD) energy, new substrate-triggered ESD protection structures are proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structures. From the experimental results, the new designs have proven a more effective ESD robustness. Moreover there is no need to add any extra mask or do any process modification for the new structures. The proposed new substrate-triggered structures have been verified in foundry’s 0.18-μm CMOS process.     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。     

On the uncertainty in the current waveform measurement of an ESDgenerator

The uncertainty in the current waveform measurement of an electrostatic discharge (ESD) generator is evaluated. The measurands are the current amplitude and the rise time of the output current waveform of the ESD generator. An intuitively simple model is proposed to evaluate the uncertainty in the current amplitude measurement. Type A and Type B evaluations for all contributions to the measurement uncertainty are performed to obtain the combined standard uncertainty. The evaluated expanded uncertainty (95.5% confidence level) of the current amplitude and the rise time at ESD voltages of 2, 4, 6, and 8 kV are within the specification of IEC 61000-4-2. The results show that the uncertainty in the current amplitude measurement stems from the voltage reading of the measuring equipment, the difference between the displayed and the actual voltages of the discharge tip of the ESD generator, and the inaccuracy of the delta time measurement of an oscilloscope, whereas the uncertainty in the rise time measurement mainly originates from the measuring equipment     

Characterization of human Metal ESD reference discharge event and correlation of generator parameters to failure levels-part I: reference event

Electrostatic discharge (ESD) generators are used for testing the robustness of electronics toward ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. Using only a few parameters, this standard specifies the peak current, the rise time and the falling edge. Lacking a transient field specification, test results vary depending on which generator is used, even if the currents are quite similar. Such a specification is needed to improve the test repeatability. As for the current, the specification should be based on a reference human metal ESD event. While keeping the presently set peak current and rise time values, such a reference ESD (5 kV, 850-/spl mu/m arc length) is identified and specifications for current derivative, fields, and induced voltages are derived. The reference event parameters are compared to typical ESD generators.     

Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors

Electrostatic discharge (ESD) failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. In general, the gate-to-contact spacing of salicided devices is known to have little impact on their ESD strength. However, experimental results presented in this paper show that the ESD strength depends on the gate-to-contact spacing independent of the silicided process. Subsequently, a detailed investigation of the influence of gate-to-source and gate-to-drain contact spacings is carried out for a salicided 0.13-/spl mu/m technology which provides new insight into the behavior of deep submicron ESD protection devices. It is shown that the reduction in current localization and increase in the power dissipating volume with increase in the gate-to-contact spacings are the primary causes of this improvement, which implies that even for silicided processes, the gate-to-contact spacing should be carefully engineered for efficient and robust ESD protection designs.     

防静电工作表面：发展和历史（一）

这篇文章对防静电工作台的发展和历史进行了回顾。静电放电工作台由支撑结构和被设计成经由接地导体使静电电荷消散的一个专门的薄层工作表面组成。防静电工作表面已成为防止静电损坏的第一道防线。这篇文章描述的工作表面发展历史与ESD市场和技术总的增长是并行发展的。当代工作台材料的历史开始于20世纪80年代早期薄板制品铝层的引入。此后不久,具有特殊表面电导率的高压三聚氰胺薄片投入使用。     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

电极移动速度效应的空气动力学分析

基于空气动力学原理解释了电极向靶运动过程中放电间隙形成局部低真空的机理.结合小间隙放电的双过程模型, 初步阐释了气体压强变化对放电间隙内部相关电参量的影响机理, 进而分析电极速度对放电参数的影响.基于我们团队自主研制的电极移动速度效应检测仪,进行反复实验, 对大量的试验数据进行仿真分析, 探索小间隙静电放电过程中放电参数对电极移动速度的依赖性.结果表明:电极移动速度与放电电流峰值、放电电流脉冲上升速度, 具有高度的正相关性; 与放电电流脉冲下降速度具有高度的负相关性.研究结果对于推进非接触静电放电测试标准的提出具有一定的参考意义.     

$hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition

For electronic applications, we have fabricated VO₂ thin-film variable resistors (varistors) using metal-insulator transition regarded as the abrupt current jump. The increase of the number of parallel stripe patterns in the varistor leads to the increase in current below a current-jump voltage, which endures a high surge voltage with high current and short rising time. Electrostatic discharge (ESD) experiments show that the varistic coefficient of 500 is larger than 30-80, which is known for commercial ZnO varistors. In overvoltage-protection tests applying high ESD voltages up to 3.3 kV to a varistor, the maximum response voltage is lower than 200 V at an ESD voltage of 1600 V, and the electronic response time is less than 20 ns. This is sufficient to protect a device perfectly.     

Determination of discharge current equation parameters of ESD using genetic algorithms

In the literature there is an absence of an accurate equation describing the current of the electrostatic discharge (ESD) phenomenon. Reported, is a method that is a genetic algorithm, which having as input data current measurements from ESD generators optimises the parameters of the discharge current's equation.     

一种系统级封装的ESD保护技术

介绍了一种系统级封装(SiP)的ESD保护技术.采用瞬态抑制二极管(TVS)构建合理的ESD电流泄放路径,实现了一种SiP的ESD保护电路.将片上核心芯片的抗ESD能力从HBM 2 000 V提升到8 000 V.SiP ESD保护技术相比片上ESD保护技术,抗ESD能力提升效果显著,缩短了开发周期.该技术兼容原芯片封...     

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

Electrostatic discharge(ESD) phenomena involve both electrical and thermal effects,and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability.Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors(BJTs) under ESD conditions has been investigated theoretically and experimentally.100 samples have been tested for multiple pulses until a failure occurred.Meanwhile,the distributions of electric field,current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici.There is a good agreement between the simulated results and failure analysis.In the case of a thermal couple,the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects.The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure.When the ESD level increased to 1.3 kV,the collector-base junction has been burnt out first.The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic.In addition,fatigue phenomena are observed during ESD testing,with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.     

Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.     

静电放电作用下微波双极型晶体管的失效机理研究

通过理论建模和试验测试的方法研究了多指结构微波双极型晶体管在静电放电作用下的热稳定性和电稳定性。选择2SC3356作为受试器件,对100个测试样本进行人体模型静电放电注入实验,并从器件内部电场强度、电流密度和温度分布变化出发,用二维器件级仿真软件辅助分析了在静电放电应力下其内在损伤过程与机理。由于指间热耦合的存在,雪崩电流在各指上分布不均,局部的电流拥挤和过热效应会导致晶格损伤。试验结果表明,由于特殊的物理结构,受试器件对静电放电最敏感的端对并不是EB结,而是CB结,当静电放电电压增大到1.3KV时,CB结首先损坏。失效分析进一步表明静电放电引起的失效机理通常是介质层的击穿和局部铝硅共晶体的过热融化。静电放电注入实验的过程中存在积累效应,多次低强度的注入测试会导致潜在性失效并使器件性能大幅下降。     

Damage analysis in smart-power technology electrostatic discharge (ESD) protection devices

Electrostatic discharge (ESD) stress - induced damage is analyzed in smart-power technology ESD protection devices. The lateral position of the ESD damage in diode and npn transistor protection structures is analyzed by using backside infrared microscopy. The lateral extension of the ESD damage is correlated with the magnitude and shape of the IV characteristics. The vertical position of the ESD damage and its stress-induced progress from the surface contact region to the bulk is obtained from the analysis of the stress-evolution of both the reverse and forward leakage current characteristics and from numerical analysis. The damage penetration into the zero-bias space charge region of the breakdown-voltage controlling pn junction is indicated by the onset of the increase of the forward leakage current.     

用于ESD防护的PDSOI NMOS器件高温特性

研究了基于0.18μm部分耗尽型绝缘体上硅(PDSOI)工艺的静电放电(ESD)防护NMOS器件的高温特性。借助传输线脉冲(TLP)测试系统对该ESD防护器件在30~195℃内的ESD防护特性进行了测试。讨论了温度对ESD特征参数的影响,发现随着温度升高,该ESD防护器件的一次击穿电压和维持电压均降低约11%,失效电流也降低近9.1%,并通过对器件体电阻、源-体结开启电压、沟道电流、寄生双极结型晶体管(BJT)的增益以及电流热效应的分析,解释了ESD特征参数发生上述变化的原因。研究结果为应用于高温电路的ESD防护器件的设计与开发提供了有效参考。