Nonvolatile memory characteristics of solution-processed oxide thin-film transistors using Ag nanoparticles

We developed a nonvolatile memory device based on a solution-processed oxide thin-film transistor (TFT) with Ag nanoparticles (NPs) as the charge trapping layer. We fabricated the device using a soluble MgInZnO active channel on a SiO₂ gate dielectric, Ag NPs as a charge trapping site at the gate insulator-channel interface, and Al for source and drain electrodes.The transfer characteristics of the device showed a high level of clockwise hysteresis that can be used to demonstrate its memory function, due to electron trapping in the Ag NPs charge trapping layer. A large memory window (?V_th) was observed with a forward and backward gate voltage sweep, and this memory window was increased in size by increasing the gate voltage sweep. These results show the potential application of memory on displays and disposable electronics.     

Visualization of charges stored in the floating gate of flash memory by scanning nonlinear dielectric microscopy

By applying scanning nonlinear dielectric microscopy (SNDM), we succeeded in clarifying that electrons existed in the poly-Si layer of the floating gate of a flash memory. The charge accumulated in the floating gate can be detected by SNDM as a change in the capacitance of the poly-Si (floating gate) by scanning the surface of the SiO(2)-SiN(4)-SiO(2) (ONO) film covering the floating gate. There was a clear black contrast region in the SNDM image of the floating gate area, where electrons were injected. However, no clear contrast appeared in the floating gate where electrons were not injected. We confirmed that SNDM is one of the most useful methods of observing the charge accumulated in flash memory.     

Low-frequency noise in nanoscale ballistic transistors

Low-frequency "1/f" noise is a major issue for nanoscale devices such at carbon nanotube transistors. We show that nanoscale ballistic transistors give voltage-dependent sensitivity to the intrinsic potential fluctuations from nearby charge traps. A distinctive dependence on gate voltage is predicted, without reference to the number of carriers. This dependence is confirmed by comparison with recent measurements of nanotube transistors. Possible ways of decreasing the noise are discussed.     

A figure of merit for optimization of nanocrystal flash memory design

Nanocrystals can be used as storage media for carriers in flash memories. The performance of a nanocrystal flash memory depends critically on the choice of nanocrystal size and density as well as on the choice of tunnel dielectric properties. The performance of a nanocrystal memory device can be expressed in terms of write/erase speed, carrier retention time and cycling durability. We present a model that describes the charge/discharge dynamics of nanocrystal flash memories and calculate the effect of nanocrystal, gate, tunnel dielectric and substrate properties on device performance. The model assumes charge storage in quantized energy levels of nanocrystals. Effect of temperature is included implicitly in the model through perturbation of the substrate minority carrier concentration and Fermi level. Because a large number of variables affect these performance measures, in order to compare various designs, a figure of merit that measures the device performance in terms of design parameters is defined as a function of write/erase/discharge times which are calculated using the theoretical model. The effects of nanocrystal size and density, gate work function, substrate doping, control and tunnel dielectric properties and device geometry on the device performance are evaluated through the figure of merit. Experimental data showing agreement of the theoretical model with the measurement results are presented for devices that has PECVD grown germanium nanocrystals as the storage media.     

Free‐Standing 2D Hexagonal Aluminum Nitride Dielectric Crystals for High‐Performance Organic Field‐Effect Transistors

The existence of defects and traps in a transistor plays an adverse role on efficient charge transport. In response to this challenge, extensive research has been conducted on semiconductor crystalline materials in the past decades. However, the development of dielectric crystals for transistors is still in its infancy due to the lack of appropriate dielectric crystalline materials and, most importantly, the crystal morphology required by the gate dielectric layer, which is also crucial for the construction of high‐performance transistor as it can greatly improve the interfacial quality of carrier transport path. Here, a new type of dielectric crystal of hexagonal aluminum nitride (AlN) with the desired 2D morphology of combing thin thickness with large lateral dimension is synthesized. Such a suitable morphology in combination with the outstanding dielectric properties of AlN makes it promising as a gate dielectric for transistors. Furthermore, ultrathin 2,6‐diphenylanthracene molecular crystals with only a few molecular layers can be prepared on AlN crystal via van der Waals epitaxy. As a result, this all‐crystalline system incorporating dielectric and semiconductor crystals greatly enhances the overall performance of a transistor, indicating the importance of minimizing defects and preparing high‐quality semiconductor/dielectric interface in a transistor configuration.     

Using chemical-mechanical polishing for planarizing a high-kappa nanocomposite polyimide insulator for organic thin film transistors application

To solve the large leakage current of the heavily blended nanocomposite (Polyimide and nano-TiO2 particles) gate dielectric film exhibiting a high-kappa, the chemical-mechanical polishing (CMP) was adopted to flatten the surface of the PI-TiO2 nanocomposite film. An extremely high dielectric constant (is congruent to 13) of the nanocomposite with CMP treatment is obtained and its leakage current is comparable to that of the neat polyimide in our studies. An OTFT based on the nanocomposite gate dielectric exhibiting high capacitance and a smooth surface after CMP treatment shows very promising performance. Compared with the OTFT based on the neat polyimide gate dielectric, the threshold voltage is improved from -22 to -5 (V), the sub-threshold voltage is decreased from 3.44 to 0.50 (V/dec), the current on/off ratio is increased from 1.6 x 10(6) to 3.53 x 10(8), and the mobility is increased from 0.416 to 0.624 (cm2V(-1)s(-1)). Moreover, it is worth noting that the hysteresis effect of OTFT based the nanocomposite can be significantly reduced due to the few charge trapped in the interface when the nanocomposite dielectric surface was further polished by CMP treatment.     

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

Device Physics of Solution‐Processed Organic Field‐Effect Transistors

Field‐effect transistors based on solution‐processible organic semiconductors have experienced impressive improvements in both performance and reliability in recent years, and printing‐based manufacturing processes for integrated transistor circuits are being developed to realize low‐cost, large‐area electronic products on flexible substrates. This article reviews the materials, charge‐transport, and device physics of solution‐processed organic field‐effect transistors, focusing in particular on the physics of the active semiconductor/dielectric interface. Issues such as the relationship between microstructure and charge transport, the critical role of the gate dielectric, the influence of polaronic relaxation and disorder effects on charge transport, charge‐injection mechanisms, and the current understanding of mechanisms for charge trapping are reviewed. Many interesting questions on how the molecular and electronic structures and the presence of defects at organic/organic heterointerfaces influence the device performance and stability remain to be explored.     

A dielectric-modulated field-effect transistor for biosensing

Interest in biosensors based on field-effect transistors (FETs), where an electrically operated gate controls the flow of charge through a semiconducting channel, is driven by the prospect of integrating biodetection capabilities into existing semiconductor technology. In a number of proposed FET biosensors, surface interactions with biomolecules in solution affect the operation of the gate or the channel. However, these devices often have limited sensitivity. We show here that a FET biosensor with a vertical gap is sensitive to the specific binding of streptavidin to biotin. The binding of the streptavidin changes the dielectric constant (and capacitance) of the gate, resulting in a large shift in the threshold voltage for operating the FET. The vertical gap is fabricated using simple thin-film deposition and wet-etching techniques. This may be an advantage over planar nanogap FETs, which require lithographic processing. We believe that the dielectric-modulated FET (DMFET) provides a useful approach towards biomolecular detection that could be extended to a number of other systems.     

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail.     

Electrostatics of nanowire transistors

The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show that charge density on the nanowire is a sensitive function of the contact geometry. For a nanowire transistor with large gate underlaps, charge transferred from bulk electrodes can effectively "dope" the intrinsic, ungated region and allow the transistor to operate. Reducing the gate oxide thickness and the source/drain contact size decreases the length by which the source/drain electric field penetrates into the channel, thereby, improving the transistor characteristics.     

Charging of molecules during transport

The possibility that a single molecule can acquire charge during steady-state transport is an open issue. We report first-principles calculations in a range of configurations of certain molecules and conclude the following. When a molecule is strongly coupled to the electrodes, charging is not sustainable. On the other hand, by using variable-length tunnel barriers (insulating tethers) one can enable and control charging. In particular, by using different combinations of "tethers", we demonstrate the possibility of charging by a single electron, sustainable over a wide bias range, and also the possibility of continuous linear charging when a gate voltage is applied.     

Tunable Fröhlich polarons in organic single-crystal transistors

In organic field-effect transistors (FETs), charges move near the surface of an organic semiconductor, at the interface with a dielectric. In the past, the nature of the microscopic motion of charge carriers--which determines the device performance--has been related to the quality of the organic semiconductor. Recently, it was discovered that the nearby dielectric also has an unexpectedly strong influence. The mechanisms responsible for this influence are not understood. To investigate these mechanisms, we have studied transport through organic single-crystal FETs with different gate insulators. We find that the temperature dependence of the mobility evolves from metallic-like to insulating-like with increasing dielectric constant of the insulator. The phenomenon is accounted for by a two-dimensional Fr?hlich polaron model that quantitatively describes our observations and shows that increasing the dielectric polarizability results in a crossover from the weak to the strong polaronic coupling regime. This represents a considerable step forward in our understanding of transport through organic transistors, and identifies a microscopic physical process with a large influence on device performance.     

Gate coupling and charge distribution in nanowire field effect transistors

We have modeled the field and space charge distributions in back-gate and top-gate nanowire field effect transistors by solving the three-dimensional Poisson's equation numerically. It is found that the geometry of the gate oxide, the semiconductivity of the nanowire, and the finite length of the device profoundly affect both the total amount and the spatial distribution of induced charges in the nanowire, in stark contrast to the commonly accepted picture where metallic dielectric properties and infinite length are assumed for the nanowire and the specific geometry of the gate oxide is neglected. We provide a comprehensive set of numerical correction factors to the analytical capacitance formulas, as well as to numerical calculations that neglect the semiconductivity and finite length of the nanowire, that are frequently used for quantifying carrier transport in nanowire field effect transistors.     

Enhanced Subthreshold Slopes in Large Diameter Single Wall Carbon Nanotube Field Effect Transistors

The performance of single wall carbon nanotube field effect transistors (SWNT FETs) is greatly affected by the quality of its contacts. The presence of Schottky barriers imposes a strong scaling of the gate dielectric thickness. Here, we employ large diameter SWNTs in order to fabricate ohmically contacted FETs when a lower work function but higher adhesion strength metal such as Cr is used. A subthreshold slope as low as 113 mV/dec is obtained even when employing a thick, 200 nm SiO$_{2}$ dielectric. The result is examined in light of the positive effects of exposure to air and underlines the possibility for less stringent device fabrication techniques.      

Three-dimensional electrostatic effects of carbon nanotube transistors

We explore the three-dimensional (3-D) electrostatics of planar-gate carbon nanotube field-effect transistors (CNTFETs) using a self-consistent solution to the Poisson equation with equilibrium carrier statistics. We examine the effects of the gate insulator thickness and dielectric constant and the source/drain contact geometry on the electrostatics of bottom-gated (BG) and top-gated (TG) devices. We find that the electrostatic scaling length is mostly determined by the gate oxide thickness, not by the oxide dielectric constant. We also find that a high-k gate insulator does not necessarily improve short-channel immunity because it increases the coupling of both the gate and the source/drain contact to the channel. It also increases the parasitic coupling of the source/drain to the gate. Although both the width and the height of the source and drain contacts are important, we find that for the BG device, reducing the width of the 3-D contacts is more effective for improving short channel immunity than reducing the height. The TG device, however, is sensitive to both the width and height of the contact. We find that one-dimensional source and drain contacts promise the best short channel immunity. We also show that an optimized TG device with a thin gate oxide can provide near ideal subthreshold behavior. The results of this paper should provide useful guidance for designing high-performance CNTFETs.     

Graphene gate electrode for MOS structure-based electronic devices

We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.     

Bistable charge configuration of donor systems near the GaAs(110) surfaces

In gated semiconductor devices, the space charge layer that is located under the gate electrode acts as the functional element. With increasing gate voltage, the microscopic process forming this space charge layer involves the subsequent ionization or electron capture of individual dopants within the semiconductor. In this Letter, a scanning tunneling microscope tip is used as a movable gate above the (110) surface of n-doped GaAs. We study the build-up process of the space charge region considering donors and visualize the charge states of individual and multi donor systems. The charge configuration of single donors is determined by the position of the tip and the applied gate voltage. In contrast, a two donor system with interdonor distances smaller than 10 nm shows a more complex behavior. The electrostatic interaction between the donors in combination with the modification of their electronic properties close to the surface results in ionization gaps and bistable charge switching behavior.     

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter.