Charge pumping in SOS—MOS transistors

The variation of the floating-substrate potential of SOS-MOS transistors is studied by applying frequent pulses to the gate. The minority carriers are injected into the floating substrate by charge pumping and they recombine there. The injected charges are stored because of the reverse-biased junctions at the source and drain. The threshold-voltage change by the substrate bias is also investigated. If the silicon film is fully depleted under the gate, the threshold-voltage change does not occur. This condition is used to stabilize the high-speed operations of the SOS-MOS integrated circuits. A new memory cell consisting of only one transistor without a storage capacitor is realized utilizing the change of the floating-substrate potential by the charge pumping and the avalanche multiplication. The sensitivity of the memory cell is affected by the channel length of an SOS-MOS transistor. The memory storage time is obtained as 300 µs.     

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.     

Improving Switching Performance of Thin-Film Transistors in Disordered Silicon

The silicon integrated electronics on glass or plastic substrates attracts wide interests. The design, however, depends critically on the switching performance of transistors, which is limited by the quality of silicon films due to the materials and substrate process constraints. Here, the ultrathin channel device structure is proposed to address this problem. In a previous work, the ultrathin channel transistor was demonstrated as an excellent candidate for ultralow power memory design. In this letter, theoretical analysis shows that, for an ultrathin channel transistor, as the channel becomes thinner, stronger quantum confinement can induce a marked reduction of OFF-state leakage current (I_OFF), and the subthreshold swing (S) is also decreased due to stronger control of channel from the gate. Experimental results based on the fabricated nanocrystalline silicon thin-film transistors prove the theoretical analysis. For the 2.0-nm-thick channel devices, I_ON/I_OFF ratio of more than 10¹¹ can be achieved, which can never be obtained for normal thick channel transistors in disordered silicon.     

单电子晶体管的制备、集成与电路研究

我们制备出了高温Si单电子晶体管,研究了单电子晶体管的集成原理,实现了14个单电子晶体管的串联集成和2个单电子晶体管的并联集成。同时也研究了单电子晶体管与传统高迁移率晶体管的集成和技术,发现可用单个电子来调控传统晶体管的栅对源漏极电流的控制能力（跨导）,利用单电子晶体管的集成方法,建立了对电荷超敏感的探测技术（包括超敏感的库尔计）,实现了单电子存储器中的单电子过程的探测,并设计了一种新型的多值存储器。     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.     

Planarization of amorphous silicon thin film transistors by liquidphase deposition of silicon dioxide

A planarized device structure was developed for amorphous silicon thin film transistors to overcome the gate leakage problem. Utilizing the liquid phase deposition technique, a silicon oxide film with thickness exactly equal to the gate height was grown around the gate to planarize the surface for the fabrication of inverted staggered thin film transistors. The planarized thin film transistor has smaller leakage current and better performance, i.e., field effect mobility, subthreshold swing, etc. This novel process has a potential to improve the yield of large area liquid crystal display     

Tunnel field-effect transistors with graphene channels

The lack of an OFF-state has been the main obstacle to the application of graphene-based transistors in digital circuits. Recently vertical graphene tunnel field-effect transistors with a low OFF-state current have been reported; however, they exhibited a relatively weak effect of gate voltage on channel conductivity. We propose a novel lateral tunnel graphene transistor with the channel conductivity effectively controlled by the gate voltage and the subthreshold slope approaching the thermionic limit. The proposed transistor has a semiconductor (dielectric) tunnel gap in the channel operated by gate and exhibits both high ON-state current inherent to graphene channels and low OFF-state current inherent to semiconductor channels.     

A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a1-micrometer silicon-film-on-insulator-on-silicon

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device     

Transistor scaling with constant subthreshold leakage

A model for scaling transistors with constant subthreshold leakage is presented. In contrast with other scaling theories, the scaling formulation presented does not necessarily lead to transistors with long channel characteristics. Instead, the transistor is scaled only to enhance circuit performance while meeting circuit specifications-in this case, subthreshold leakage current. The model is critically dependent upon the drain induced barrier lowering effect which has been evaluated as a function of channel length, gate thickness, and channel doping. The effect is found to vary asL^{-m}wherem = 1.2-1.4.     

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in strong inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.     

双栅无结型场效应晶体管的设计与优化

利用三维数值仿真工具,对双栅无结型场效应晶体管进行了数值模拟,研究了沟道掺杂浓度深度分布对晶体管性能的影响,并对比分析了当沟道长度缩小到10nm及以下时器件的电学特性。仿真结果表明,相比于沟道为均匀掺杂分布的器件,具有中间低的沟道掺杂深度分布的双栅无结型场效应晶体管具有更优的开关电流比、漏致势垒降低、亚阈值斜率等电学性能和短沟道特性。     

UDSM subthreshold leakage model for NMOS transistor stacks

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered.Compared to SPICE simulations using PTM's BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32 nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

A semianalytical model of a thin-channel field-effect transistor

A semianalytical model of a field-effect ballistic nanotransistor with an ultrathin channel, which is used to describe transistors with both single and double gates, is suggested. The potential distributions and the electron concentrations in the transistor channel are calculated in terms of this model. The afterthreshold and subthreshold volt-ampere characteristics are plotted. A comparison with a more correct numerical model is given.     

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.     

场引晶体管理论:XI.双极电化电流（薄及厚、纯及不纯基体,单及双MOS栅极）

场引晶体管本质双极,包括电子和空穴表面和体积沟道和电流,一或多个外加横向控制电场．自1952年Shockley发明,55年来它被认为单极场引晶体管,因电子电流理论用多余内部和边界条件,不可避免忽略空穴电流．多余条件,诸如电中性和常空穴电化电势,导致仅用电子电流算内部和终端电学特性的错误解．当忽略的空穴电流与电子电流可比,可在亚阈值区和强反型区,错误解有巨大误差．本文描述普适理论,含有电子和空穴沟道和电流．用z轴宽度方向均匀的直角平行六面体（x,y,z）晶体管,薄或厚、纯或杂基体,一或二块MOS栅极,描述两维效应及电势、电子空穴电化电势的正确内部和边界条件．没用多余条件,导出四种常用MOS晶体管,直流电流电压特性完备解析方程：半无限厚不纯基上一块栅极（传统的Bulk MOSFET）,与体硅以氧化物绝缘的不纯硅薄层上一块栅极（SOI）,在沉积到绝缘玻璃的不纯硅薄层上一块栅极（SOI TFT）,和薄纯基上两块栅极（FinFETs）．     

多晶硅薄膜晶体管亚阈值区准二维模型(英文)

从准二维泊松方程出发,结合多晶硅扩散和热发射载流子输运理论,建立了多晶硅薄膜晶体管亚阈值电流模型。由表面势方程及亚阈值电流方程求得包含陷阱态和晶粒尺寸的亚阈值斜率解析表达式。模型具有简明的表达式,并且在大晶粒和低陷阱态情形下可简化为传统长沟道MOSFET亚阈值区模型。仿真结果与试验数据符合得很好,验证了模型的正确性。     

Numerical analysis of a cylindrical thin-pillar transistor(CYNTHIA)

The authors have analyzed the characteristics of a cylindrical thin-pillar transistor, (CYNTHIA), which is a vertical MOS transistor with a cylindrical gate electrode surrounding a submicrometer-diameter silicon pillar. The device characteristics are calculated by solving Poisson's equation in cylindrical coordinates. Results showed that CYNTHIA has three superior features: excellent subthreshold characteristics, enhanced electron mobility, and increased sheet electron concentration. These superior characteristics result in a feature size twice that of vertical SOI transistors, The authors' calculation is that CYNTHIA is quite an attractive device design for future ultra-high-density LSIs     

The effects of impurity redistribution of the subthreshold leakage current in CMOS n-channel transistors

A study of subthreshold leakage current in n-channel transistors on low threshold voltage CMOS circuits has been made. Redistribution of impurities at the silicon surface during thermal oxidation is shown to be the main cause of excess subthreshold leakage current. Processing techniques to minimize this leakage have been developed.