Multi-Value Voltage-to-Voltage Converter Using a Multi-Stage Symmetrical Charge Pump for On-Chip EEPROM Programming

A fully integrated multi-stage symmetrical structure chargepump and its application to a multi-value voltage-to-voltage converterfor on-chip EEPROM programming are presented. The multi-valuevoltage-to-voltage converter is designed to offer two output voltages,power supply and triple power supply alternatively, which is neededfor a memory array. A dynamic analysis of the multi-stage symmetricalstructure charge pump and an optimization design in terms of circuitarea are also given. The circuit is implemented in a 1.2 CMOSprocess and the measurement results show that a voltage pulse as shortas 5 s with a rise time of 3 s is obtained. For a 5 V powersupply and with a resistive charge of 100 k, the programmingoutput voltage can reach as high as 11 V and output current forprogramming is over 110 A, which are high enough to program thememory cell.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

A New Approach to Realize Variable Gain Amplifiers

A new methodology to develop variable gain amplifiers is developed. The methodology is based on a feedback loop to generate the exponential characteristic, which is required for VGA circuits. The proposed idea is very suitable for applications that require very low power consumption, and as an application, a new current mode variable gain amplifier will be shown. The gain is adapted via a current signal ranges from –7.5 A to +6.5 A. Pspice simulations based on Mietec 0.5 m CMOS technology show that the gain can be varied over a range of 29.5 dB, with bandwidth of 3 MHz at maximum gain value. The circuit operates between ±1.5 V and consumes an average amount of power less than 495 W.     

Low-Power Low-Voltage Class-AB Linear OTA for HF Filters with a Large Tuning Range

This letter presents a new low-voltage class-AB differential linear OTA. The proposed transconductor uses a novel scheme based on two cross-coupled class-AB pseudo-differential pairs biased by a Flipped Voltage Follower [1]. The transconductor has been designed using a 0.8 m CMOS technology to operate at 2 V supply voltage with only 260 W of quiescent power consumption. Simulation results show 90 MHz bandwidth with more than two decades of transconductance tuning range.     

Synthesis of Log-Domain Filters from First-Order Building Blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.     

An Analog Correlator for a WCDMA Receiver

A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 m×686 m and the current drain is approximately 370 A.     

A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption.     

A Low-Power Block-Matching Cell for Video Compression

This paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 mtechnology and the measured energyconsumption is 1.2 nJ per block match usingan pixel matrix. Simulations ofthe same cell in 0.35 m and 0.25 mCMOS technology are presented, showing thescalability of the approach.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

A CMOS Offset Phase Locked Loop for a GSM Transmitter

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.     

A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 m×73 m in a 2-m CMOS process and can retain charge accuracy for over 25 years.This research was partially supported by DARPA under Contracts MDA972-90-C-0037 and MDA972-88-C-0048 and by TRW, Inc.     

A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 m, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 m CMOS technologies. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

Personal Imaging and lookpainting as tools for personal documentary and investigative photojournalism

A means and apparatus for covert capture of extremely highresolution photorealistic images is presented. The apparatus embodies a new form of userinterface – instead of the traditional point and click metaphor which was thought to be the simplest photography had to offer, what is proposed is a look metaphor in which images are generated through the natural process of looking around, in a manner that does not require conscious thought or effort. These lookpaintings become photographic/videographic memories that may, at times, exceed the quality attainable with even large and cumbersome professional photographic film cameras, yet they may be captured through a device that resembles ordinary sunglasses. The method is based on longterm psychophysical adaptation using a covert sunglassbased realitymediating apparatus, together with two new results in image processing. The first new result is a means of estimating the true projective coordinate transformation between successive pairs of images, and the second is that of estimating, to within a single unknown scalar constant, the quantity of light arriving at the image plane. Furthermore, what is captured is more than just a picture. The resulting environment map may be explored by one or more remote participants who may also correspond and interact with the wearer during the actual shooting process, giving rise to computer supported collaborative (collective) photography, videography, shared photographic/videographic memory, etc.     

1D GaAs Detector Arrays for Digital X-ray Imaging with a 108-μm Spatial Resolution

A 1D x-ray detector array of pitch 108 m is designed, fabricated, and tested. The array is based on the p⁺–n–n–n⁺ structure made in epitaxial GaAs technology. Guard rings are incorporated to reduce detector cross coupling. It is announced that the technology proposed will be used to make arrays with a pitch of 50 m and a spatial resolution of 10 line-pairs/mm, suitable for digital mammography.     

Surface-Photovoltage Measurement of Volume Electron Lifetime in p-Si Wafers

The problem of estimating the volume lifetime _v of minority carriers in p-type Si wafers by surface-photovoltage measurements is addressed. An experiment is conducted in order to ascertain the relationship between measured and actual values of _v. The measurements are carried out on circular specimens whose thickness is reduced from about 2000 to 450 m by stepwise etching. The specimens are cut from a Czochralski-grown rod, their actual values of _v ranging from 10 to 300 s. The surface recombination rate of minority carriers is determined on both sides of the specimens covered with native oxide, the sides differing in surface finish. The results of the experiment allow one to determine _v up to about 400 s.     

Current Testing Procedure for Deep Submicron Devices

This paper presents a test technique that employs two different supply voltages for the same IDDQ pattern. The results of the two measurements are subtracted in order to eliminate the inherent sub-threshold leakage. Summary of the experiment carried out on System on a Chip (SOC) device build in 0.35 technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit IDDQ.