A novel interface circuit for triboelectric nanogenerator

For most triboelectric nanogenerators (TENGs), the electric output should be a short AC pulse, which has the common characteristic of high voltage but low current. Thus it is necessary to convert the AC to DC and store the electric energy before driving conventional electronics. The traditional AC voltage regulator circuit which commonly consists of transformer, rectifier bridge, filter capacitor, and voltage regulator diode is not suitable for the TENG because the transformer''s consumption of power is appreciable if the TENG output is small. This article describes an innovative design of an interface circuit for a triboelectric nanogenerator that is transformerless and easily integrated. The circuit consists of large-capacity electrolytic capacitors that can realize to intermittently charge lithium-ion batteries and the control section contains the charging chip, the rectifying circuit, a comparator chip and switch chip. More important, the whole interface circuit is completely self-powered and self-controlled. Meanwhile, the chip is widely used in the circuit, so it is convenient to integrate into PCB. In short, this work presents a novel interface circuit for TENGs and makes progress to the practical application and industrialization of nanogenerators.     

一种新型的用于高速串行接口的数据处理电路

本文提出了一种新型的用于USB2.0高速模式下(480Mbps的数据传送率)的数据处理电路.这种电路采用八位并行的方法将数据转换为USB协议规定的数据格式,包含一个高速、低功耗的并串转换电路及一个八分频电路.芯片设计基于TSMC公司的0.25μmCMOS混合信号模型,采用半定制(semi-custom)的设计流程.电路的前后仿真结果表明该数据处理电路达到了480MHz的传输速度,符合USB2.0的要求.     

Line and receiver interface circuit for high-speed voice-band modems

A single-chip implementation of the analog signal processing functions required for full-duplex voice-band modem operation over twisted pair wires is described. Echo path signal-to-signal harmonic distortion plus noise exceeds 65 dB. The device is implemented in a 3.5-/spl mu/m twin-tub CMOS process, and typically dissipates 180 mW.     

A high-speed median circuit

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-μm CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm ², and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor     

A novel high-speed CMOS circuit based on a gang of capacitors

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with V_DD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.     

高速DAC与正交调制器接口电路设计

结合宽带数字TR组件零中频发射波形产生思想,设计了高速DAC与正交调制器的接口电路。给出详尽设计方法及步骤的同时使用TINA—TI软件对设计的接口电路进行了交直流特性及宽带信号幅频特性仿真,验证了其正确性。     

基于Sepic电路的工业照明设备节能电源设计

在照明领域,LED发光产品的应用正吸引着世人的目光,LED作为一种新型的绿色光源产品,必然是未来发展的趋势。 LED驱动电源作为LED照明的核心技术之一,功率因数及效率一直偏低,成为阻碍LED照明工程化应用推广的主要瓶颈。基于Sepic拓扑并带有功率因数校正的LED驱动电源不仅能有效地提高功率因数及效率,降低无功损耗,同时对于节能减耗、降低成本也有非常重要的意义。     

A circuit for high-speed time switching

A method of time switching for time-division communication systems is introduced. A compact shift register-based circuit is used for this purpose in order to achieve high-speed switching     

Integrated wiring system for construction equipment

Advances in electronic technology have brought numerous changes in design of most types of construction equipment. Due to the electronic devices and electric loads, such as lamps and motors, a typical construction vehicle has many wires and connectors. The next phase of the changes is to focus on how to reduce these complex wires by using digital communications. This paper presents the development of an integrated wiring system for construction equipment. More specifically, an excavator that has more than 40 devices has been chosen in order to apply the concept of the integrated wiring system. After grouping electrical devices by their locations and functions, two communication controllers, i.e., an instrument controller and an engine-hydraulic controller, are defined. Two test controllers have been developed in order to prove the concept     

基于CPCI系统的高速数字通信接口电路设计与应用

随着航空电子系统的迅速发展,系统间频繁的信息交换和共享对数据传输实时性和可靠性的要求日益提高。针对这一要求,提出了一种基于CPCI系统下实现AFDX协议端系统接口功能的方法,为通用信号处理平台与AFDX网络的连接提供接口,实现AFDX协议数据的高速、可靠性传输。给出了采用FPGA实现该功能的整体方案,详细描述了基于FPGA硬件开发的各个模块的设计,介绍了基于Micro Blaze的嵌入式软件设计方法,在EDK中采用C语言实现AFDX协议IP层以上的封装和解封装。最后经过仿真验证和测试,验证了设计的正确性。     

A novel circuit for accurate characterization and modeling of thereverse recovery of high-power high-speed rectifiers

As circuit switching frequency continues to increase, there is a need to produce faster rectifiers with lower power losses. Efficient utilization of high-power ultrafast rectifiers requires precise knowledge of the key static and dynamic switching parameters, especially the reverse-recovery characteristics. Conventional reverse-recovery test circuits were developed to test rectifiers with reverse-recovery times (t_RR) greater than 100 ns, however, new measurement techniques are needed for accurate characterization and modeling of the high-power ultrafast rectifier reverse-recovery process. A test circuit topology is proposed which offers several advantages over existing test circuits. This circuit offers the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/dt. This circuit is also studied using a two-dimensional (2-D) mixed device and circuit simulator in which the device under test is represented as a 2-D finite-element grid and the semiconductor equations are solved under boundary conditions imposed by the proposed test circuit. This simulation tool is used to understand the device physics of the reverse-recovery process and develop more accurate models to be implemented in behavioral circuit simulators. The simulation results are then compared to the measured data for a silicon P-i-N and 200-V GaAs Schottky rectifier under various measurement conditions. Simulation results are shown to be in excellent agreement with the measured data     

A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.     

A novel high-speed fourier-vector processor

A special purpose processor is added to a signal processor, developed at the Lehrstuhl für Nachrichtentechnik, University of Erlangen-Nürnberg for computation of FFT, inverse FFT, and vector operations. The design and implementation of the so-called Fourier-Vector Processor is reported on. The specifications, especially speed and accuracy are investigated. The application for a short-time spectrum analysis using a polyphase filter bank is described as an example.     

DAB接收机中的低相位噪声低功耗高速数模混合下分频模块

本文实现了一种用于DAB数字广播调谐器的具有低相位噪声与低功耗的高速数模混编下分频模块。在设计中采用了若干项新的电路技术以提升电路的性能。采用了具有改进型源极耦合逻辑D触发器的同步分频器与具有改进型CMOS主从触发器的异步分频器实现了具有低相位噪声的双模分频器。在吞吐式计数器的设计中采用了一种更为精确的线负载模型。电路采用0.18-?m CMOS工艺实现。芯片面积为0.6mm?0.2mm。下分频模块中的双模分频器的输出信号在距载波中心频率10kHz频偏处的相位噪声仅为-118.2dBc/Hz。下分频模块的核心部分在1.8V供电电源下的功耗仅为2.7mW。     

浅谈维修电工线路板的接线技巧

根据教学实践经验,提出中级维修电工培训中的接线技巧,对如何提高学生的接线技能进行阐述,在实践教学中取得良好的效果。     

A monolithic telephone subscriber loop interface circuit

An integrated circuit that interfaces a subscriber loop with the digital telephone exchange has been produced with conventional high-voltage IC technology. The monolithic SLIC controls DC loop current, converts signal transmission from two-wire to four-wire, and suppresses longitudinal induction. Bias control circuitry automatically reduces standby power when subscriber equipment is detected on-hook. High-voltage circuit techniques maintain performance when the supply voltage exceeds the n-p-n transistor BV/SUB CE0/, and circuit partitioning with two discrete transistors yields manageable junction temperature and an economical 102/spl times/112 mil die size.     

高速电路的板层设计

本文给出了高速电路的板层设计方法，重点研究了信号的高频回流和电源层的设计。在电源设计中研究了电源的分割和数模电源设计。文中给出了电源分割模型，并根据这个模型结合信号源的设计实例进行了详细的叙述，具有重要的工程实践意义。     

高速电路的印制板(PCB) 仿真

简要描述了印制电路板的仿真过程，分析仿真对于设计高质量、高精度PCB的重要意义，并在场景产生器的PCB板上使用仿真工具对关键信号(时钟信号)进行信号完整性和EMC分析，以及并行信号的串绕问题分析，根据仿真结果调整了原有设计，从而达到提高了信号质量的目的。     

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50 ps width with ~17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Giga-sample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.