A Three-Level Resonant Single-Stage Power Factor Correction Converter: Analysis, Design, and Implementation

This paper presents a new single-stage power factor correction ac/dc converter based on a three-level half-bridge resonant converter topology. The proposed circuit integrates the operation of the boost power factor preregulator and the three-level resonant dc/dc converter. A variable-frequency asymmetrical pulsewidth modulation controller is proposed for this converter. This control technique is based on two integrated control loops: the output voltage is regulated by controlling the switching frequency of the resonant converter, whereas the dc-bus voltage and input current are regulated by means of duty cycle control of the boost part of the converter. This provides a regulated output voltage and a nearly constant dc-bus voltage regardless of the loading condition; this, in turn, allows using smaller switches and consequently having a lower on resistance helping to reduce conduction losses. Zero-voltage switching is also achieved for a wide range of loading and input voltage. The resulting circuit, therefore, has high conversion efficiency making it suitable for high-power wide-input-voltage-range applications. The effectiveness of this method is verified on a 2.3-kW 48-V converter with input voltage (90–265 Vrms).      

Lagrangian modeling and passivity-based control of three-phase AC/DC voltage-source converters

In this paper, we investigate the dc-bus voltage regulation problem for a three-phase boost-type pulsewidth-modulated (PWM) ac/dc converter using passivity-based control theory of Euler-Lagrange (EL) systems. The three-phase PWM ac/dc converters modeled in the a-b-c reference frame are first shown to be EL systems whose EL parameters are explicitly identified. The energy-dissipative properties of this model are fully retained under the d-q-axis transformation. Based on the transformed d-q EL model, passivity-based controllers are then synthesized using the techniques of energy shaping and damping injection. Two possible passivity-based feedback designs are discussed, leading to a feasible dynamic current-loop controller. Motivated from the usual power electronics control schemes and the study of Lee, the internal dc-bus voltage dynamics are regulated via an outer loop proportional plus integral (PI) controller cascaded to the d-axis current loop. Nonlinear PI control results of Desoer and Lin are applied to theoretically validate the proposed outer loop control scheme. The PWM ac/dc converter controlled by the proposed passivity-based current control scheme with outer loop PI compensation has the features of enhanced robustness under model uncertainties, decoupled current-loop dynamics, guaranteed zero steady-state error, and asymptotic rejection of constant load disturbance. Experimental results on a 1.5-kVA PC-based controlled prototype provide verification of these salient features. The experimental responses of a classical linear PI scheme are also included for comparative study.     

Performance evaluation of an FPGA controlled soft switched inverter

A field programmable gate array (FPGA) based controller is proposed for a dc link series resonant inverter. The basic operation of the zero current switching inverter is briefly described. A strategy of decoupling the control of the dc link current from the load current is identified and referred as decoupled current control (DCC). The use of gate-controlled devices like metal-oxide-semiconductor field-effect transistor/insulated gate bipolar transistor/MOS-controlled thyristor permits a higher resonance frequency at the link of the inverter. The increased frequency enables the application of pulse density modulation technique with a bang-bang controller to synthesise and control the wave-shapes of current and voltage of the inverter. The DCC strategy eliminates the conventional analogue controller. A digital sequence controller has been designed using the state machine technique for the reliable operation of the inverter. The digital design is implemented on a single chip FPGA. To verify the proposed control strategy and the FPGA controller, a prototype has been built and tested. The test results show that a sinusoidal inverter output voltage is maintained with total harmonic distortion less than 5% and a regulation of about 1% from no-load to full-load, including non-linear and transient loads. The performance of the inverter with the FPGA controller is promising and attractive for uninterrupted power supply applications.     

Active input-voltage and load-current sharing in input-series and output-parallel connected modular DC-DC converters using dynamic input-voltage reference scheme

This paper explores a new configuration for modular DC/DC converters, namely, series connection at the input, and parallel connection at the output, such that the converters share the input voltage and load current equally. This is an important step toward realizing a truly modular power system architecture, where low-power, low-voltage, building block modules can be connected in any series/parallel combination at input or at output, to realize any given system specifications. A three-loop control scheme, consisting of a common output voltage loop, individual inner current loops, and individual input voltage loops, is proposed to achieve input voltage and load current sharing. The output voltage loop provides the basic reference for inner current loops, which is modified by the respective input voltage loops. The average of converter input voltages, which is dynamically varying, is chosen as the reference for input voltage loops. This choice of reference eliminates interaction among different control loops. The input-series and output-parallel (ISOP) configuration is analyzed using the incremental negative resistance model of DC/DC converters. Based on the analysis, design methods for input voltage controller are developed. Analysis and proposed design methods are verified through simulation, and experimentally, on an ISOP system consisting of two forward converters.     

Step-by-step design procedure for a grid-connected three-phase PWM voltage source converter

The voltage source active rectifier is one of the most interesting solutions to interfacing dc power systems to the grid. Many elements are responsible for the overall system behaviour, such as value of the passive elements, sensors position, analog/digital filters and ac current/dc voltage controllers. In this paper a step-by-step design procedure, taking into account all these elements, is proposed and validated through the tests on an experimental prototype. The reported results are particularly relevant to evaluate the influence on the grid current harmonic content of the grid sensor position and of the use of analog filters in the feedback signals.     

Practical Implementation of a High-Frequency Current-Sense Technique for VRM

To track the inductor current in high-frequency dc/dc converters is not effortless, particularly when high output currents and low output voltages are demanded by the load. This paper proposes a simple technique to obtain a good accuracy in the inductor current measurement in voltage regulator module (VRM) applications. The main idea is to obtain an equivalent voltage image which can be used for the high-frequency pulsewidth modulation controller to generate the converter control law. This strategy of measurement is generic, and it has been previously validated by simulations. Afterward, some experimental results are obtained by using several prototypes of dc/dc converters delivering a very low output voltage and owning several loads from 10-mA to 100-A currents. This wide range covers the power requirements of portable and embedded VRM applications. Moreover, this sense technique has also been validated in a digital high-frequency current-mode-controlled dc/dc converter.      

Design, analysis, and real-time testing of a controller for multibus microgrid system

This paper concentrates on the design and analysis of a controller for multibus microgrid system. The controller proposed for use with each distributed generation (DG) system in the microgrid contains inner voltage and current loops for regulating the three-phase grid-interfacing inverter, and external power control loops for controlling real and reactive power flow and for facilitating power sharing between the paralleled DG systems when a utility fault occurs and the microgrid islands. The controller also incorporates synchronization algorithms for ensuring smooth and safe reconnection of the micro and utility grids when the fault is cleared. With the implementation of the unified controller, the multibus microgrid system is able to switch between islanding and grid-connected modes without disrupting the critical loads connected to it. The performance of this unified controller has been verified in simulation using a real-time digital simulator and experimentally using a scaled laboratory prototype.     

A Minimal Harmonic Controller for a STATCOM

In this paper, a novel controller with fixed modulation index (MI) and variable dc capacitor voltage reference to minimize voltage and current harmonics is presented for a distribution static synchronous compensator (STATCOM). The STATCOM with the proposed controller consists of a three-phase voltage-sourced inverter and a dc capacitor and is used to provide reactive power compensation and regulate ac system bus voltage with minimum harmonics. A systematic design procedure based on pole-zero cancellation, root locus method, and pole assignment method has been developed to determine proper parameters for the current regulator, the dc voltage controller, and the ac voltage controller of the STATCOM. With the proposed STATCOM controller, harmonic distortions in the inverter output current and voltage can be reduced since the MI is held constant at unity in steady state. In addition, a fast adjustment in the STATCOM output reactive power is achieved to regulate the ac bus voltage through the adjustment of the dc voltage reference during the transient period. Simulation and experimental results for the steady-state operating condition and transient operating conditions for the system subjected to a reactive current reference step change, a three-phase line to neutral fault, and a step load change are presented to demonstrate the effectiveness of the proposed controller.     

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

Paralleled DSP-based soft switching-mode rectifiers with robust voltage regulation control

This paper presents the current sharing and robust voltage regulation controls for paralleled digital signal processor-based soft switching-mode rectifiers (SSMRs). First, the design and implementation of single-module SSMRs are made. In dealing with the current control loop design of each SSMR module, the small-signal model is derived and used to design the current-controlled pulse-width modulation (PWM) scheme. As to the common voltage control loop, its dynamic model is estimated from measurements. Then, a quantitative design procedure is developed to find the parameters of the voltage controller according to the prescribed control specifications. As the changes of parallel number and operating condition occur, the robust control is added to reduce the voltage regulation control performance degradation. The proposed multimodule operation control scheme consists of a master controller and N slave controllers. The former further consists of a common voltage controller and a current distribution unit, and the latter are the current-controlled PWM schemes of all SSMRs. Each slave controller receives the weighted sinusoidal current command from the master controller and regulates the feedback current of SSMR. The results confirm that the designed parallel SSMR system possesses good line drawn current power quality, module current sharing and voltage regulation control performances.     

A direct digital control for the phase-controlled rectifier

Direct digital control of the phase-controlled rectifier (PCR) is implemented with a minimum control hardware structure. A digital phase-locked voltage control (PLVC) without detecting the line voltage is presented. An inner fast control loop is proposed to stabilize the PCR system and to obtain its constant loop gain. In the inner loop, an averaging function is introduced to feed back the average DC voltage of the PCR output without the feedback filter. Its synchronism is modeled and analyzed. An optimal constant digital integral, proportional, and measurable variable feedback (IPM) current controller with a time-multiplied performance index is also proposed to obtain a good dynamic response of the output current. All control functions are implemented with an Intel 8797 single-chip microcomputer. Experimental results show that the scheme gives good dynamic and static performance for the PCR system     

Implementation of a Three-Phase Capacitor-Clamped Active Power Filter Under Unbalanced Condition

A capacitor-clamped voltage-source inverter for active power filter operation under balanced and unbalanced conditions is proposed to suppress current harmonics and compensate the reactive power generated from the nonlinear loads. The adopted voltage-source inverter is based on a three-level capacitor-clamped topology to reduce the voltage stress of power semiconductors. Two control loops are used in the control scheme to achieve harmonic and reactive currents compensation and to regulate the inverter dc side voltage. In the adopted inverter, the neutral point voltage is compensated by a voltage compensator to obtain the balanced capacitor voltages on the dc side. In order to control the flying capacitor voltages, two redundant states in each inverter leg can be selected to compensate the flying capacitor to obtain a better voltage waveform with low harmonic contents on the ac terminals. The balanced and sinusoidal line currents are drawn from the ac source under the balanced and unbalanced conditions. The feasibility of the proposed scheme is confirmed through experimental results     

A critical analysis of Z-source converters considering the effects of internal resistances

Nowadays Z-source networks are the most promising power converter networks that cover almost all electric power conversion (dc–dc, dc–ac, ac–dc and ac–ac) applications. However, the controller design is critical for Z-source converter (ZSC) due to the presence right-half-plane zero (RHPZ) in the control-to-capacitor-voltage transfer function. This RHPZ exhibits non-minimum phase undershoot in the capacitor voltage and also in the dc-link voltage waveforms. A perfect small-signal model is required to predict locations of the RHP zero and its dynamics. This paper contributes towards the small-signal analysis of ZSC under continuous conduction mode considering the parasitic resistance of the inductor, equivalent series resistance of the capacitor, internal resistances of active switch and forward voltage drop of the diode. The maximum allowable value of shoot-through duty ratio (STDR) and voltage gain for different values of the internal resistance and load resistance are discussed in this paper. The accuracy of the developed small-signal average model is compared with detailed circuit model in MATLAB/SIMULINK. Finally, the steady-state simulation results of ZSC are validated with hardware results.     

Control of distributed generation systems-Part I: Voltages and currents control

This paper discusses a digital control strategy for three-phase pulse-width modulation voltage inverters used in a single stand-alone ac distributed generation system. The proposed control strategy utilizes the perfect robust servomechanism problem control theory to allow elimination of specified unwanted voltage harmonics from the output voltages under severe nonlinear load and to achieve fast recovery performance on load transient. This technique is combined with a discrete sliding mode current controller that provides fast current limiting capability necessary under overload or short circuit conditions. The proposed control strategy has been implemented on a digital signal processor system and experimentally tested on an 80-kVA prototype unit. The results showed the effectiveness of the proposed control algorithm.     

Analysis and Design for a Novel Single-Stage High Power Factor Correction Diagonal Half-Bridge Forward AC–DC Converter

By means of components placement, the buck-boost and diagonal half-bridge forward converters are combined to create a novel single-stage high power factor correction (HPFC) diagonal half-bridge forward converter. When both the PFC cell and dc–dc cell operate in DCM, the proposed converter can achieve HPFC and lower voltage stress of the bulk capacitor. The circuit analysis of the proposed converter operating in$ DCM+ DCM$mode is presented. In order to design controllers for the output voltage regulation, the ac small-signal model of the proposed converter is derived by the averaging method. Based on the derived model, the proportional integral (PI) controller and minor-loop controller are then designed. The simulation and experimental results show that the proposed converter with the minor-loop controller has faster output voltage regulation than that with the PI controller despite the variations of line voltage and load. Finally, a 100-W prototype of the proposed ac–dc converter is implemented and the theoretical result is experimentally verified.     

Low Frequency Architecture for Multi-Lamp CCFL Systems With Capacitive Ignition

A low frequency architecture is proposed for driving parallel cold cathode fluorescent lamps (CCFLs) in large screen liquid crystal display (LCD) TV backlighting applications. Key to the architecture is a proposed capacitive coupling approach for aiding lamp ignition. A dc voltage is applied to the lamp electrodes while an ac voltage is applied to an external plate for capacitive coupling. The result is reliable, simultaneous ignition of parallel lamps with a required applied dc voltage near the lamp steady-state operating voltage. The complete system architecture includes a single high voltage converter, a pulse lamp ignition circuit, current control circuits and a single backlight controller. The topology is capable of driving a large number of parallel lamps with independent lamp current regulation, while avoiding ac coupling losses in steady-state operation and achieving significant reduction in reactive components when compared to typical high frequency ac ballast designs. Experimental results are presented for a system of four parallel 250 mm length lamps, demonstrating simultaneous parallel lamp ignition and dc current regulation.     

Optimal controller design for a matrix converter based surface mounted PMSM drive system

This paper proposes a new control algorithm for a matrix converter permanent magnet synchronous motor (PMSM) drive system. First, a new switching strategy, which applies a backpropagation neural network to adjust a pseudo DC bus voltage, is proposed to reduce the current harmonics of the permanent magnet synchronous motor. Next, a two-degree-of-freedom controller is proposed to improve the system performance. The parameters of this controller are obtained by using a frequency-domain optimization technique. The controller design algorithm can be applied in an adjustable speed control system and a position control system to obtain good transient responses and good load disturbance rejection abilities. The controller design procedures require only algebraic computation. The implementation of this kind of controller is only possible by using a high-speed digital signal processor. In this paper, all the control loops, including current-loop, speed-loop, and position-loop, are implemented by a 32-b TMS320C40 digital signal processor. The hardware, therefore, is very simple. Several experimental results are shown to validate the theoretical analysis.     

Optimal Predictive Control of Three-Phase NPC Multilevel Converter for Power Quality Applications

This paper presents the optimal control of the ac currents, the dc voltage regulation, and the dc capacitor voltage balancing in a three-level three-phase neutral point clamped multilevel converter for use in power quality applications as an active power filter. The ac output currents and the dc capacitor voltages are sampled and predicted for the next sampling time using linearized models and considering all the 27 output voltage vectors. A suitable quadratic weighed cost function is used to choose the voltage vector that minimizes the ac current tracking errors, the dc voltage steady-state error, and the input dc capacitor voltage unbalancing. The obtained experimental results show that the output ac currents track their references showing small ripple, a total harmonic distortion (THD) of less than 1%, harmonic contents that are 46 dB below the fundamental, and almost no steady-state error (0.3%). The capacitor voltages are balanced within 0.05%, and the balancing is assured even when redundant vectors are not chosen. Near-perfect capacitor dc voltage balancing is obtained while reducing current harmonic distortion. Some experimental evidence of robustness concerning a parameter variation was also found, with the optimum controller withstanding parameter deviations from $+$100% to $-$50%. Compared to a robust sliding mode controller, the optimal controller can reduce the THD of the ac currents or reduce the switching frequency at the same THD, being a suitable controller for power quality in medium-voltage applications.      

A Seamless Mode Transfer Maximum Power Point Tracking Controller For Thermoelectric Generator Applications

A boost-cascaded-with-buck converter-based power conditioning system employing a seamless mode transfer maximum power point tracking controller is proposed to maximize energy production of a thermoelectric generator while balancing a vehicle battery, alternator output power, and vehicle load. When a vehicle battery is fully charged, the proposed controller switches to a power matching mode seamlessly by a dual loop control system, which detects the input and output voltages and currents of the boost-cascaded-with-buck converter, and adjusts the commands accordingly. Both voltage and current loops are designed in a frequency domain using small signal models to ensure stable operation. A mode selection and voltage and current commands are determined by a digital signal processor-based controller. The experimental results with a dynamic source and load steps are presented to show the effectiveness of the proposed approach.      

Identification, digital control and fuzzy logic techniques applied to a synchronous generator

The experimental results obtained in the design and implementation of an decoupled digital speed and voltage controller for a micro-energy system are reported in this work. The studied system is formed by a 9 Kw DC motor driving a 10 KVA synchronous machine. There are two control loops in the proposed controller: the speed control (speed governor) and the control of the stator's voltage (automatic voltage regulator). Each control loop was designed using linear control techniques and fuzzy control techniques. Tests on the system show the performance of the proposed controllers.