A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

A novel technique is proposed to characterise the charge trapping properties of MOS capacitors by using the gate voltage ramping test. The parameter I=1-I/sub g/(t)/I/sub s/(t+ Delta t) measured during gate voltage ramping reveals the dielectric charge trapping characteristics. Positive charge trapping before dielectric breakdown was observed using this technique. A comparison between I and flatband voltage shift, Delta V/sub fb/, indicates that I gives the same information as Delta V/sub fb/ does at high stress fluences.<>     

Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.     

Effect of long-term stress on IGFET degradations due to hot electron trapping

The threshold voltage shift through the long-term stress is measured for IGFET's. The gate bias dependence shows that the hot electron trapping is affected strongly by the electric field in the gate insulator. The threshold voltage shift versus time is well explained with the theory modified by the effect of the trapped charge on the subsequent electron trapping. The effect of transistor dimensions and temperature are also discussed.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed     

Reliability issues of offset drain transistors after different modes of static electrical stress

The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO₂ interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

New positive charge trapping dynamics in SiO2 gate oxide, based on bulk impact ionization processes under Fowler–Nordheim stress

A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO₂) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.     

Impact of interface and bulk trapped charges on transistor reliability

Oxide reliability is a key issue and the main topic of several recent works. We study the impact of gate oxide stress on transistor performances following a methodology similar to oxide lifetime characterisation in capacitors. A universal trend for degradation of the threshold voltage and drain saturation current with injected charge is observed and the impact of boron on trapping enhancement has been separated by comparing n-MOS and p-MOS.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

Improved reliability of HfO/sub 2//SiON gate stack by fluorine incorporation

Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO/sub 2//SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V/sub th/, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.     

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (V_th) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the V_th shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer.     

Charge Trapping and TDDB Characteristics of Ultrathin MOCVD HfO2 Gate Dielectric on Nitrided Germanium

In this letter, we investigate the long-term reliability characteristics of ultrathin HfO₂ dielectrics on nitrided germanium for the first time. Stress-polarity dependence in charge trapping and time-dependent dielectric-breakdown (TDDB) characteristics has been observed in germanium nand p-type devices. The p-MOS devices exhibit severe charge trapping under stress, while no significant charge trapping and stress-induced leakage current were found in the n-MOS devices. In terms of operation-voltage projection for a ten-year lifetime, V_g=2.8 and -2.1 V is projected for the germanium p- and n-MOS devices, respectively, with an equivalent oxide thickness of 11 Aring. Compared to Si control samples, germanium devices show a comparable projected operation voltage, indicating that the TDDB for high-kappa dielectrics on nitrided germanium is not a concern. The stress-polarity dependence in germanium devices is believed to result from the asymmetrical band structure and the significant difference of the electric field strength across the gate dielectric between the positive and negative stress conditions     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.