High-frequency submicrometerAl0.48In0.52As/In0.53Ga0.47As heterostructure bipolar transistors

The high speed scaling of an Al_0.48In_0.52As/In_0.53Ga_0.47 As submicrometer heterostructure bipolar transistor (HBT) is presented. Transistors with emitter dimensions of 0.5×11 and 3.5×3.5 μm² exhibit unity current-gain cutoff frequencies of 63 and 70 GHz, respectively. Emitter current density greater than 3.3×10⁵ A/cm² is demonstrated in a submicrometer AlInAs/InGaAs HBT. The analysis shows that the device speed is limited by the parasitic collector charging time     

Down-scaling differential pairs of depleted optical thyristors

We present the results of a scaling study of monolithic differential pairs of optical thyristors. The devices are depleted thyristors, intended for high-frequency and high-sensitivity operation. According to the measurements, the optical switching energy scales with area and equals to 15 aJ/μm². The smallest pair with mesas of 10×15 μm² operates with 2.6 fJ of light input. Sub-femtojoule optical switching energy is expected in the near future     

The effects of geometrical scaling on the frequency response andnoise performance of SiGe HBTs

We examine the geometrical scaling issues in SiGe HBT technology. Width Scaling, length scaling, and stripe-number scaling are quantified from a radio frequency (RF) design perspective at 2 GHz. We conclude that a SiGe HBT with emitter area A_E=0.5×20×6 μm² is optimum for low noise applications at J_c=0.1 mA/μm² and f=2 GHz using the design methodology, which guarantees optimal noise and input impedance matching with the simplest matching network. Finally, the optimal device sizes at f=4 and 6 GHz for low noise applications are also obtained using the same method     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f_T) of 207 GHz and an f_MAX extrapolated from Mason's unilateral gain of 285 GHz. f_MAX extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12×2.5 μm² have these characteristics at a linear current of 1.0 mA/μm (8.3 mA/μm²). Smaller transistors (0.12×0.5 μm²) have an f_T of 180 GHz at 800 μA current. The devices have a pinched base sheet resistance of 2.5 kΩ/sq. and an open-base breakdown voltage BV_CEO of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f_T at small lateral dimensions     

Submicrometre gate length scaling of inversion channelheterojunction field effect transistor

The scaling to 0.5 μm of the inversion channel HFET with a single strained InGaAs quantum well is described. A unity current gain frequency of 40 GHz, g_m=205 mS/mm and V_TH=-0.34 V have been obtained for 0.5×100 μm² devices. For shorter gate lengths, threshold shifts are sizeable so that in order to scale further, modifications to the growth and processing are required     

Fully-planar AlGaAs/GaAs HBT's achieved by selective CBE regrowth

This paper describes a novel fully planar AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology using selective chemical beam epitaxy (CBE). Planarization is achieved by a selective regrowth of the base and collector contact layers. This process allows the simultaneous metallization of the emitter, base and collector on top of the device. For the devices with an emitter-base junction area of 2×6 μm² and a base-collector junction area of 14×6 μm², a current gain cut off frequency of 50 GHz and a maximum oscillation frequency of 30 GHz are achieved. The common emitter current gain h_FE is 25 for a collector current density J_c of 2×10⁴ A/cm²     

Stable single-mode operation of an 850-nm VCSEL with a higher ordermode absorber formed by shallow Zn diffusion

We report that an 850-nm vertical-cavity surface-emitting laser with a planar higher order mode absorber, formed by shallow Zn diffusion (<0.3 μm), operated at stable single-mode over the entire drive current range. A device with a 5×5 μm² absorber aperture and a 5×5 μm² oxide confined active region showed a ~0.8 mA threshold and a mode suppression ratio of 40 dB. The modeling indicates that the higher order modes will be suppressed strongly due to the much larger threshold gain, compared to that of the fundamental mode as long as the Zn diffusion depth outside the 5×5 μm² absorber aperture is over ~0.2 μm, which agrees well with the experimental results     

Submicrometer self-aligned AlGaAs/GaAs heterojunction bipolartransistor process suitable for digital applications

A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm². The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF₃. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm² at submilliampere collector currents. The maximum f_T and f_max obtained from a 0.5×2 μm² emitter HBT are 46 and 42 GHz, respectively at I_C=1.5 and more than 20 GHz even at I_C=0.1 mA     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

Low temperature microwave characteristics of 0.1 μm gate-lengthpseudomorphicIn0.52Al0.48As/InxGa1-xAs(x=0.85 and 0.95) MODFET's

We have studied the microwave characteristics of 0.1 μm gate-length pseudomorphic In_0.52Al_0.48As/In_x Ga_1-xAs (x=0.85 and 0.95) modulation-doped field-effect transistors (MODFET's) at 300 K and lower temperatures down to 77 K. A maximum f_T of 151 GHz has been measured for a 0.1×55 μm² gate In_0.52Al_0.48As/In_0.85 Ga_0.15As MODFET at 77 K and this represents an improvement of 33% over the room temperature value. This behavior has been analyzed     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

Performance enhancement of GaInP/GaAs heterojunction bipolarphototransistors using dc base bias

GaInP-GaAs heterojunction bipolar phototransistors grown by metal organic vapor phase epitaxy (MOVPE) and operated with frontside optical injection through the emitter are reported with high optical gain (<88) and record high frequency performance (28 GHz). Heteropassivation of the extrinsic base surface is employed using a depleted GaInP emitter layer between the nonself-aligned base contact and the emitter mesa. The phototransistor's performance is shown to improve with increasing dc base bias in agreement with predictions of a recently reported Gummel-Poon model. Experimental results are reported for devices with optical active areas of 10×10 μm², 20×20 μm², and 30×30 μm², with peak measured cutoff frequencies of 28.5, 23.1, and 18.5 GHz, respectively, obtained at collector current densities between 2×10 ³ and 6×10³ A/cm²     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation     

High-performance, 0.1 μm InAlAs/InGaAs high electron mobilitytransistors on GaAs

This letter describes the material characterization and device test of InAlAs/InGaAs high electron mobility transistors (HEMTs) grown on GaAs substrates with indium compositions and performance comparable to InP-based devices. This technology demonstrates the potential for lowered production cost of very high performance devices. The transistors were fabricated from material with room temperature channel electron mobilities and carrier concentrations of μ=10000 cm² /Vs, n=3.2×10¹² cm^-2 (In=53%) and μ=11800 cm²/Vs, n=2.8×10¹² cm^-2 (In=60%). A series of In=53%, 0.1×100 μm² and 0.1×50 μm² devices demonstrated extrinsic transconductance values greater than 1 S/mm with the best device reaching 1.074 S/mm. High-frequency testing of 0.1×50 μm² discrete HEMT's up to 40 GHz and fitting of a small signal equivalent circuit yielded an intrinsic transconductance (g_m,i) of 1.67 S/mm, with unity current gain frequency (f_T) of 150 GHz and a maximum frequency of oscillation (f_max) of 330 GHz. Transistors with In=60% exhibited an extrinsic g_m of 1.7 S/mm, which is the highest reported value for a GaAs based device     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm² memory cell. The macro size of the LL4T-SRAM is 56 mm², which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell     

Frequency multiplier measurements on heterostructure barriervaractors on a copper substrate

We have fabricated heterostructure barrier varactors (HBV) on a copper substrate, which offers reduced spreading resistance, and improved thermal conductivity compared to an InP substrate. The devices are fabricated without degrading the electrical characteristics. The three-barrier HBV material grown by MOVPE has a leakage current of only 0.1 μA/μm² at 19 V. The maximum capacitance is 0.54 fF/μm². In a frequency tripler experiment a maximum output power of 7.1 mW was generated at 221 GHz with a flange-to-flange efficiency of 7.9%