FSO通信误码测试仪硬件设计

介绍了一种基于AT89S52单片机和EP1K30 FPGA的FSO通信误码测试系统的设计与实现方案.系统以FPGA为处理核心,实现高速误码检测;单片机完成控制逻辑.详细讨论了伪随机码发生模块、同步模块、误码检测模块及单片机与FPGA接口的软硬件设计.并利用设计的样机进行了本地光纤环回和实验室内近距离无线激光通信的误码测试实验,实验结果表明此设计工作稳定可靠,可以实现对FSO通信质量进行检测的设计要求.     

基于ARM Cortex-M3的高速误码测试系统设计

误码测试仪是评估通信信道的测试仪器.基于国内高速误码测试仪空缺、国外高速误码仪价格昂贵的现状,提出一种新的基于ARM Cortex-M3微处理器LM3S9B90和10 Gbit/s光收发器SI5040的简易、低廉的高速误码测试系统.经测试,该系统在保持成本低廉的同时还有较好的误码测试性能.     

SDH光传输误码测试仪方案设计

文章介绍了一种基于LPC2478 CPU和XC3S1500 FPGA的光传输误码测试仪的方案设计。该测试仪以FPGA为数据处理核心,完成误码检测;CPU为控制核心,完成系统初始化和逻辑控制。详细描述了SDH信号处理模块、控制模块、时钟同步模块、误码检测模块的软硬件设计。并利用设计的样机和进口仪器ANT-5进行了对测,对多批次SDH设备进行了误码测试,测试结果表明此设计方案稳定可靠,实现了对SDH光传输设备误码检测的设计要求。     

一种基于FPGA的高速误码测试仪的设计

误码测试仪是检测通信系统可靠性的重要设备。传统的误码测试仪基于CPLD和CPU协同工作,不仅结构复杂,价格昂贵,而且不方便携带。基于FPGA的高速误码测试仪,采用FPGA来完成控制和测试模块的一体化设计,提高了系统功能扩展性和系统的集成度,使得各个功能模块在不改动硬件电路的情况下可以相应变化。在发送端发送m序列作为测试数据,其测试速率最高可达到155 Mb/s。由于将物理层上的各协议层的功能集中到FPGA内部实现,减少了硬件和软件的设计复杂度,并且缩短了系统的开发的周期,具有可升级的特点。     

基于OFDM的LDPC误码测试系统设计

通过比较国内外几种LDPC误码平台测试系统,设计了一种基于OFDM的用于测试LDPC解码误码性能的窄带系统,采用了时域同步正交频分复用调制方式,具有抵抗多径干扰和多普勒频移的能力.该系统用FPGA予以实现,不仅可用于实验室测试,也可用于测试真实多径环境下的误码性能,还能作为通用系统用于其他信道纠错码的解码误码测试.     

误码测试仪设计与实现

本文讨论了一种基于DSP、FPGA和触摸屏的误码测试仪的设计与实现。DSP实现对测试系统的控制,FPGA完成误码判别与计数,触摸屏提供人机操作交互界面。本文重点讨论了系统硬件FPGA设计和软件DSP设计,测试结果表明该误码测试仪工作稳定可靠,可实现对传输设备通信质量的检测。     

一种宽带无线接入系统的信道编码及其实现

介绍一种适合于宽带无线接入系统采用的信道煽码设计方案。为了实现实时高速数据传输，该设计通过硬件方式加以实现。调试及测试结果表明，该方案对于克服无线接入中的误码具有良好的性能。     

基于FPGA的2M误码测试仪设计

根据2M误码测试仪的系统整体功能要求．给出了基于FPGA的2M误码测试仪的系统硬件架构和核心控制器FPGA内核的设计框架。重点介绍了系统硬件结构中E1接口的设计方法和软件中的系统时钟模块、测试序列发生模块、位同步信号提取模块和帧同步信号检测模块的FPGA设计方法。同时以Ahera的QuartusⅡ软件为开发平台,给出了部分模块的仿真波形图。     

SDH／SONET同步光缆传输系统的误码性能

首先介绍了光缆传输系统关于误码性能的一些基本概念，然后讨论了光缆传输系统误码性能的主要参数，并着重描述了关于块误码的基本概念及误码性能的规范标准，最后进一步明确指出的新规范标准中，对于高速光缆通道误码性能提出了更高要求，在网络系统的设计，管理中必须给予充分注意。     

紫外光通信误码率测试系统设计

为了对紫外光通信系统的传输性能进行定量分析,设计了基于FPGA的误码序列发送和接收系统,并在上位机利用labVIEW程序实现了对误码的分析和计算。该系统发射端测试序列采用9阶伪随机m序列,并按照一定的速率传送给LED驱动电路,接收端完成光电信号处理、脉冲序列同步和数据提取,格式化后通过串口发送至上位机进行误码分析。室内测试结果表明,该设计适于完成紫外光通信系统误码率的分析和计算,可以为紫外光通信系统最佳链路的选择提供依据。     

一种便携式误码测试仪的设计

误码仪是数字通信系统性能测试的重要仪器。设计采用国外专用集成误码测试芯片DS2172、E1接口芯片DS21554和单片机芯片AT89C52联合设计,全部采用高效低功耗芯片,并使用单电源工作,它是一款体积小、重量轻、成本低、便携式的低速率误码测试仪。     

Hot-carrier-reliability design guidelines for CMOS logic circuits

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft_rise and 10/ft_fall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively     

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This paper investigates techniques to speed up HSSI bit-error rate and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.     

Hot-carrier-reliability design rules for translating devicedegradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at V_gs=V_ds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft_rise and 10/ft_fall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively     

一种RNN-T与BERT相结合的端到端语音识别模型

端到端语音识别模型由于结构简单且容易训练,已成为目前最流行的语音识别模型。然而端到端语音识别模型通常需要大量的语音-文本对进行训练,才能取得较好的识别性能。而在实际应用中收集大量配对数据既费力又昂贵,因此其无法在实际应用中被广泛使用。本文提出一种将RNN-T(Recurrent Neural Network Transducer,RNN-T)模型与BERT(Bidirectional Encoder Representations from Transformers,BERT)模型进行结合的方法来解决上述问题,其通过用BERT模型替换RNN-T中的预测网络部分,并对整个网络进行微调,从而使RNN-T模型能有效利用BERT模型中的语言学知识,进而提高模型的识别性能。在中文普通话数据集AISHELL-1上的实验结果表明,采用所提出的方法训练后的模型与基线模型相比能获得更好的识别结果。     

Zero-anaphora resolution in Korean based on deep language representation model: BERT

It is necessary to achieve high performance in the task of zero anaphora resolution (ZAR) for completely understanding the texts in Korean, Japanese, Chinese, and various other languages. Deep-learning-based models are being employed for building ZAR systems, owing to the success of deep learning in the recent years. However, the objective of building a high-quality ZAR system is far from being achieved even using these models. To enhance the current ZAR techniques, we fine-tuned a pre-trained bidirectional encoder representations from transformers (BERT). Notably, BERT is a general language representation model that enables systems to utilize deep bidirectional contextual information in a natural language text. It extensively exploits the attention mechanism based upon the sequence-transduction model Transformer. In our model, classification is simultaneously performed for all the words in the input word sequence to decide whether each word can be an antecedent. We seek end-to-end learning by disallowing any use of hand-crafted or dependency-parsing features. Experimental results show that compared with other models, our approach can significantly improve the performance of ZAR.     

基于USB 2.0的高速实时数据采集系统设计

为实现数据高速采集并将大批量数据快速传输到PC机做后续处理,设计了一种基于USB 2.0的高速实时数据采集系统。介绍了整个系统的硬件设计,详细阐述了USB接口芯片ISP1581的固件、驱动及应用程序开发。本系统设计已在高速DSP平台上得到了验证,很好地完成了数据采集、处理及传输任务。     

支持突发传输的嵌入式误码仪设计和实现

灵活方便及低成本的误码测试仪是解决卫星通信系统大范围覆盖内各种终端性能测试的有效工具。分析了误码测试仪的使用需求,提出了一种基于现场可编程门阵列(FPGA)的嵌入式误码测试仪的设计方法。该方法实现简单、硬件资源占用非常少,采用VHDL语言编写,易于嵌入到多种卫星通信终端中,支持突发传输模式下的误码测试,便于终端的自检测试及辅助系统故障定位。     

A CMOS IC for Gb/s Viterbi decoding: system design and VLSIimplementation

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the “minimized method” (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 μ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude