Study of nanocrystal memory integration in a Flash-like NOR device

Si nanocrystal memory cells have been integrated in Flash-like stand-alone devices of 16 Mb along with high and low voltage CMOS logic circuitry. Process integration drawbacks such as nanocrystal residuals in the circuitry region have been eliminated by optimizing etching processes.The program/erase threshold voltage distributions of the memory sectors are well separated and narrow. The voltage distribution width is related to NC sizes, and bigger NCs induce cell reliability problems. Some reliability issues for endurance are also related to the use of ONO dielectric which acts as charge trapping layer, mainly causing program/erase window shift and threshold voltage distribution broadening during endurance.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

Flash memory reliability

With reference to the mainstream technology, the most relevant failure mechanisms which affect yield and reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as a key factor for improving Flash memory reliability. The degradation of device performance induced by program/erase cycling is discussed, covering both the behaviour of a typical cell and the evolution of memory array distribution. The erratic erasure phenomenon is illustrated as the most relevant mechanism reported so far to cause single bit failures in endurance tests. Finally, reliability implications of multilevel cell concepts are briefly analysed.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters     

A long-refresh dynamic/quasi-nonvolatile memory device with 2-nmtunneling oxide

A memory device using silicon rich oxide (SRO) as the charge trapping layer for dynamic or quasi-nonvolatile memory application is proposed. The device achieved write and erase speed at low voltage comparable to that of a dynamic-random-access memory (DRAM) cell with a much longer data retention time. This device has a SRO charge trapping layer on top of a very thin tunneling oxide (<2 nm). Using the traps in the SRO layer for charge storage, a symmetrical write/erase characteristics were achieved. This new SRO cell has an erase time much shorter than values of similar devices reported in the literature     

Crested barrier in the tunnel stack of non-volatile memories

In this work a high-k insulating film is deposited on the SiO₂ tunnel oxide of MOS capacitors designed for non-volatile memory applications. The advantages of this approach derive from the asymmetric band diagram, which lowers the Fowler–Nordheim tunnel erase barrier, without affecting the program operation. This results in lower erase voltage and much shorter erase times. In fact, in the proposed structure the erase voltage is about 20% lower and the erase current three thousands times greater than in conventional MOS with pure-SiO₂ tunnel oxide and the same equivalent oxide thickness (15 nm). At the same time, the larger physical thickness prevents from charge loss, and guarantees data retention. The goal of such device is to improve the memory performances without degrading reliability.     

Characterization of thin-oxide MNOS memory transistors

A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices (X_{o}=25 Aring, X_{N} = 335 Aring) exhibit aDelta V_{th} = plusmn3V for an erase/writet_{p} = 100ns, which corresponds to an initial oxide field strengthE_{ox}= 1.2 times 10^{7}V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO2interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.     

Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.     

Performance Evaluation of Field-Enhanced P-Channel Split-Gate Flash Memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler–Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of$sim$2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.     

Flash memory architecture

Flash memories entered the nonvolatile memory scenario only a few years ago, and now these kind of memories are battling to substitute either EEPROM or EPROM. In fact, their peculiarities are becoming quite interesting in present day applications.In system updating, low power consumption, embedded algorithm for program and erase, high density, low cost packages are some of the items which are making the Flash grow in the nonvolatile memory market share.Some words must be spent in explaining what the market is asking of Flash, which are the main applications for these memories, and how their architecture is arranged.The Flash memory cell behaviour will be described, then the fundamental operations (read, program and erase) are explained and some words are used to introduce the redundancy and device testability concept.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Effects of erase source bias on Flash EPROM device reliability

This paper is concerned with the effects of the source bias during the erase operation on the reliability of Flash EPROM devices. It will be shown that positive charge in the tunnel oxide, mostly generated by the erase operation, is a major cause of the unintentional charge loss/gain mechanisms that disturb the data content of the memory cell. The effects of the erase source bias are evaluated in the context of the positive oxide charge generation and the resulting enhancement of the gate current that causes the data loss. An optimal source bias during erase, around 2 V for our samples, is shown to cause the least positive oxide charge. A model based on the band-to-band tunneling-induced hole generation in Si and subsequent hole injection during the erase operation is presented and discussed     

The HIMOS flash technology: the alternative solution for low-cost embedded memory

The high-injection MOS (HIMOS) technology was initially developed as an application-specific memory technology, i.e., a nonvolatile block-erasable (Flash-type) memory for embedded applications. The label "embedded" points out that cost was considered to be the prime issue. Because of this, processing complexity and voltage reduction have been the major driving forces in the cell and process development rather than mere cell size scaling. Indeed, what really counts in embedded applications is the chip area per megabit rather than the cell size itself. Because the substantially high operating voltages of floating-gate-based memories are not being scaled, the peripheral area becomes the main bottleneck for most embedded applications. Also, cost has to be viewed in terms of masking steps and complexity or marginality of processing in general, especially in the case of embedded Flash, since the envisaged products have to be incorporated in a conventional CMOS line. To achieve this goal, a split-gate approach was adopted, which, combined with an additional program gate (PG), leads to maximized hot-electron efficiency at low voltages. As an additional major advantage, this PG allows the use of an electrically erasable programmable ROM-like threshold voltage window. This implies that the high threshold needs to be only slightly positive, while the low one could be strongly negative. Such a scheme allows very low excess charge levels (especially in the more critical off state), which greatly improves device reliability, while allowing further scaling of the tunnel oxide as compared with other Flash concepts. This allows further reduction of the program/erase voltages. Also, such a window provides a larger read current, which removes the necessity for wordline boosting during readout and therefore improves access time.     

Temperature effect on read current in a two-bit nitride-based trapping Storage Flash EEPROM cell

The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V/sub T/ state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V/sub T/ state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

Flash memory goes mainstream

The operation of the flash memory, which has matured over the last five years from a novelty product, is described. Both dual and single supply voltage devices are considered. Flash memory cycling, data reliability, program/erase algorithms, and blocking are discussed. Three approaches to flash memories are examined. The uses of these devices and some new architectures are considered     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.