4 Gbit/s pseudo-noise generator using GaAs MESFETs

A multiplexing gate using GaAs MESFETs is described and operation up to 4 Gbit/s is demonstrated. A 2 Gbit/s pseudo-noise generator which can deliver NRZ or RZ signals has been implemented with this circuit; the corresponding output sequences are shown.     

10 Gbit/s AND gate using dual-gate GaAs MESFET

Using a commercial dual-gate GaAs MESFET transistor mounted in a microstrip circuit, an AND gate has been built. With the 100 ps (FWHM) wide test pulses available, a speed of 10 Gbit/s NRZ and a pulse suppression of at least 14 dB was obtained.     

All-optical 40 Gbit/s XOR gate with dual ultrafast nonlinear interferometer

A novel XOR logic gate using dual cascaded ultrafast nonlinear interferometer elements based on semiconductor optical amplifiers is proposed and demonstrated at 40 Gbit/s. The gate is switched at the line rate rather than twice line rate, as in previously reported differential XOR gates.     

500 Gbit/s optical gate monolithically integrating photodiode and electroabsorption modulator

Optical demultiplexing at a corresponding data rate of 500 Gbit/s has been achieved using an ultrafast monolithic optical gate integrating a photodiode and an electroabsorption modulator. The on/off ratio is 9 dB for adjacent channels and larger than 20 dB for other channels.     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

Multi/demultiplexing in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

Multiplexing from 1 to 2 Gbit/s and corresponding demultiplexing from 2 to 1 Gbit/s including clock regeneration and pulse width reduction has been performed using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input, clock and output signals are shown.     

High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters

A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.     

Bit synchronisation in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

Bit synchronisation at 1 and 2 Gbit/s including pulse width reduction is achieved using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input-, clock- and output signals are shown.     

Performance analysis of sub-micron gate GaAs MESFETs

A novel 2-D numerical model incorporating nonstationary electron dynamics is used to investigate the complex transport phenomena governing the operation of sub-micron gate GaAs MESFET's. A detailed theoretical analysis of different phenomena observed in subhalf micron devices is given. These include velocity overshoot, stationary and travelling domain formation, soft pinch off, excess drain current etc. The small signal parameters g_m, g_d and C_gs and their dependence on bias condition are evaluated. The effects of physical quantities such as mobility and interface barrier on carrier injection and transport and consequently on device performance are presented.     

Modeling of the gate junction in GaAs MESFETs

A low-signal equivalent circuit of a GaAs MESFET is suggested. In this circuit, the gate junction is represented so that a potential variation along the channel can be taken into account. A relationship between the gate current and the gate-source and drain-source voltages is found     

5 Gbit/s laser-driver GaAs IC

A design of a 5 Gbit/s laser-driver GaAs IC employing a novel 50 Ω impedance matched output driver is presented. Eye diagrams with good eye openings, clean waveforms and output reflection coefficients of less than -8 dB for frequencies up to 10 GHz are demonstrated over a 10-36 mA output current tuning range     

400Gbit/s高速大容量光通信系统单模光纤设计与制备

介绍了一种大有效面积单模光纤的数值设计分析与PCVD(等离子体化学气相沉积)制备工艺,该光纤的有效面积达到133μm2,同时在1 550nm处衰减系数优化到0.183dB/km,弯曲损耗优化至0.45dB/圈(弯曲半径7.5 mm)。在双偏振DFT-S CO-OFDM 4QAM/16QAM(4进制/16进制正交振幅调制的离散傅里叶变换扩展相干光正交频分复用)调制信号下,对该光纤在100Gbit/s和400Gbit/s系统的误码率和Q值等传输性能进行了验证。结果表明,该光纤能有效改善最佳入纤功率和非线性效应,可使传输距离提升30%,能有效优化400Gbit/s传输系统,并且在FTTx领域有着广泛的应用前景。     

320 Gbit/s光时分复用系统研究

针对高速率OTDM(光时分复用)系统中的一些关键技术问题,如时钟提取、时分解复用和色散补偿等,提出了8×40Gbit/s的OTDM系统技术方案。结果表明,通过选择合适的时钟提取方式和基于对称性色散位移光纤的色散补偿技术,能够实现在一个时隙内对每个信道的40 Gbit/s归零码信号的解复用,且解复用后的信号质量较好。该系统实现了320Gbit/s OTDM通信。     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

10 Gbit/s GaAs 跨阻前置放大器

GaAs基pHEMT工艺适合于制作10Gbit／s速率的高速前置放大器电路。完成了工作于10Gbit／s速率的跨阻前置放大器电路的器件设计、电路设计,电路采用了串联电感L技术,有效地提高了工作带宽。模拟工作带宽达到9．0GHz,跨阻增益达到58dBt2。电路采用0．2pmGaAs基pHEMT电子束直写T型栅工艺制作。对制作的电路进行了电测试,可工作于10Gbit／s的速率。     

4 Gbit/s GaAs MESFET laser-driver IC

A high-speed laser-driver IC has been fabricated using etched-gate enhancement/depletion-mode MESFET technology. It has been demonstrated that the device is capable of driving 25? load with 80 mA modulation current at up to 4 Gbit/s NRZ data rate.     

44 Gbit/s GaAs MESFET selector IC

A novel 2:1 selector circuit is described. To achieve high-speed operation, a parallel feedback circuit and inductor peaking were added to a conventional selector circuit. Furthermore, wide bandwidth buffers are carefully designed to cover the operation frequency of this selector circuit. The selector IC, fabricated with 0.1 μm class GaAs MESFETs, operated at up to 44 Gbit/s     

40 Gbit/s WDM系统在长途骨干网中的应用

随着业务的爆炸式增长,40 Gbit/s WDM(波分复用)系统已经在现有骨干网中大规模商用。文章分析了40 Gbit/s系统工程建设中的相关问题,包括40 Gbit/s系统的光纤选型、编码选择、40 Gbit/s系统中10 Gbit/s业务的解决方案、40 Gbit/s系统的OLP(光线路保护)和客户端解决方案。     

ODB和EDC在10Gbit/s光纤传输系统中的应用

文章介绍和分析了光双二进制的构造原理及其色散容差性能,研究了电色散补偿(EDC)技术的一般性原理. 通过220 km G.652光纤的传输试验,表明采用光双二进制编码和 EDC技术构建无光色散补偿链路的10 Gbit/s光纤传输系统的可行性.