Multi/demultiplexing in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

Multiplexing from 1 to 2 Gbit/s and corresponding demultiplexing from 2 to 1 Gbit/s including clock regeneration and pulse width reduction has been performed using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input, clock and output signals are shown.     

4 Gbit/s pseudo-noise generator using GaAs MESFETs

A multiplexing gate using GaAs MESFETs is described and operation up to 4 Gbit/s is demonstrated. A 2 Gbit/s pseudo-noise generator which can deliver NRZ or RZ signals has been implemented with this circuit; the corresponding output sequences are shown.     

Bit synchronisation in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

Bit synchronisation at 1 and 2 Gbit/s including pulse width reduction is achieved using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input-, clock- and output signals are shown.     

Multicast-enabled high-speed VCSEL technology for flexible data center networks

We experimentally demonstrate the multiple signal modulation on a single class 10 G vertical cavity surface emitting laser (VCSEL) carrier at 1 310 nm for next generation multicast-enabled data center networks. A 10 Gbit/s data signal is directly modulated onto a single mode VCSEL carrier. To maximize carrier spectral efficiency, a 2 GHz reference frequency (RF) clock tone is simultaneously modulated on the VCSEL phase attribute. The inherent VCSEL orthogonal polarization bistability with changing bias current is further exploited in transmission of a polarization based pulse per second (PPS) timing clock signal. Therefore, we simultaneously transmit a 10 Gbit/s directly modulated data, 2 GHz phase modulated RF and a polarization-based PPS clock signals using a single mode 10 GHz bandwidth VCSEL carrier. It is the first time that a single class 10 G VCSEL carrier is reported to transmit a directly modulated data, phase modulated RF clock and polarization based PPS timing signal simultaneously in a single wavelength. A of G.652 single mode fibre (SMF) transmission over 3.21 km is experimentally attained. A receiver sensitivity of ?15.60 dBm is experimentally obtained for the directly modulated 10 Gbit/s data signal. A 3.21-km-long SMF transmission introduces a penalty of 0.23 dB to the data signal. The contribution of a 2 GHz phase modulated RF and a polarization-based PPS clock signal to this penalty is found to be 0.03 dB. An RF single-side band (SSB) phase noise values of ?82.36 dBc/Hz and ?77.97 dBc/Hz are attained without and with simultaneous directly modulated data and polarization-based PPS clock signals respectively for a 3.21-km-long SMF transmission. This work provides an alternative efficient and cost effective technique for simultaneous high-speed multiple information transmission to different network nodes within a data center network through shared network infrastructure.     

6Gbit/s multiplexer and regenerating demultiplexer ICs for optical transmission systems based on a standard bipolar technology

Time-division 4:1 multiplexing and 1:4 demultiplexing as well as signal regeneration are important functions in high-speed optical fibre transmission systems. It has been shown by experiments that these tasks can be solved up to about 6Gbit/s by using monolithic integrated circuits fabricated with a 2 ?m standard bipolar technology.     

超高速单电源GaAs判决再生电路

设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .5Gbit/s系列光通信系统     

40 Gbit/s fully monolithic clock recovery IC usingInAlAs/InGaAs/InP HEMTs

The authors describe a 40 Gbit/s fully monolithic clock recovery integrated circuit (IC) fabricated using 0.1 μm InAlAs/InGaAs/InP HEMTs. The IC utilises injection locking, and consists of a half bit delay, an exclusive OR gate and a T-type flip-flop. The IC extracts a half-rate clock signal from a 39.81312 Gbit/s 2³¹-1 pseudo-random bit sequence signal without any other external components     

Optoelectronic time division multiplexing

The concept of using optoelectronic (photoconductive) switches as the sampling element in time division multiplexing is introduced in the context of VLSI off-chip data transmission. A 4:1 multiplexer was fabricated in Cr : GaAs, activated by a GaAs laser via optical fibre delay lines and operated at 2.5 Gbit/s.     

Timing Jitter Reduction by All-Optical Signal Regeneration Using a Polarization Bistable VCSEL

All-optical signal regeneration is experimentally demonstrated using a polarization bistable vertical-cavity surface-emitting laser. The retiming operation of signal regeneration is performed by using an AND gate operation and a reset operation. An optical clock pulse and input data signal are used for the AND gate operation. The timing jitter of the regenerated signal is reduced by optimizing the injection power ratio of the clock pulse and the data signal. The retiming operation is analyzed using a simple model that includes random fluctuation of the polarization switching threshold and bandwidth limitation of the response to the injection light.      

10 Gbit/s all-optical regenerator

A 10 Gbit/s optical data stream has been regenerated all-optically by clock recovery and remodulation. The regenerator consists of a fibre ring laser, modelocked by the incoming data stream, and a Kerr shutter acting as an all-optical AND gate to recode the ring laser pulses with the incoming data. Error ratio measurements for an all-optical regenerator are presented for the first time and the future potential of all-optical regeneration is discussed     

High speed GaAs digital integrated circuit with clock frequency of 4.1 GHz

A maximum clock frequency of 4.1 GHz was obtained for a GaAs digital integrated circuit using deep recess normally-on GaAs MESFETs with 1.2 ?m long gate and interdigitated Schottky diodes. The Ti/Pt/Au gate electrode was made by a lift-off technique with conventional photolithography. The minimum propagation delay of a NAND/AND gate was estimated to be 100 ps/gate for a fan-out of 2 from the self-oscillation frequency of the master-slave flip-flops.     

25 Gbit/s selector module using 0.2 mu m GaAs MESFET technology

A high-speed selector module has been developed. It is constructed from a selector IC mounted in a ceramic package, a power supply unit, phase shifters, and coaxial cables. The IC was designed using LSCFL and fabricated with 0.2 mu m gate length GaAs MESFETs. The selector module operated above 25 Gbit/s. It is expected to be applied to high-speed IC measurements.<>     

The GaAs MESFET as a pulse regenerator, amplifier, and laser modulator in the Gbit/s range

Using GaAs MESFET's under switching conditions, the regeneration and amplification of fast pulses and the modulation of semiconductor lasers in the Gbit/s speed range is performed. Sharpening factors of 3 at output pulse rise times of nearly 50 ps and voltage amplification factors of 2 at 50 /spl Omega/ are attained for output pulses up to 100 mA. The regeneration is caused by the clamping at the input port of the MESFET and by the nonlinear transconductance characteristic. In the pulse modulation mode, the laser diode is directly controlled by the MESFET. The switching behavior of the driver stage is calculated using the equivalent circuit of the laser diode and of the MESFET. This evaluation reveals that the maximum pulse rate is limited by the laser diode.     

Differential precoder IC modules for 20-and 40-Gbit/s opticalduobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-μm gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1×10^-9     

New data regeneration scheme for multi-Gbit/s fibre-optic links

A novel optical regeneration scheme without using nonlinear clock recovery elements has been demonstrated in a transmission experiment at 2.4 Gbit/s over 35 km of fibre. In this scheme, the clock is superimposed on the data signal at the transmitter end, and is separated from the composite signal by passive filters at the receiver end for data regeneration     

A novel symmetric 10 Gbit/s architecture with a single feeder fiber for WDM-PON based on chirp-managed laser

We propose the single feeder fiber architecture for wavelength division multiplexing passive optical network(WDM-PON)based on directly modulated chirp managed laser(CML).The downlink(DL)signal output from the laser is converted to return-to-zero(RZ)differential phase shift signal using a pulse carver.The downstream signal is reused as a carrier for the upstream using intensity modulation technique.Simulation results show the error-free performance at symmetric data rate of 10 Gbit/s per channel with negligible power penalty and improved receiver sensitivity for the uplink(UL),over 25 km standard single-mode fiber(SSMF).A low-cost and reduced circuitry network design is implemented on a single feeder fiber with the elimination of differential encoder and one external modulator.     

In-band clock distribution concept for ultra-high bit rates OTDM system

A novel clock distribution concept based on inband phase-modulated pilot insertion is demonstrated.This method avoids the need for an ultrafast phase comparator and a phase-locked loop in the receiver.Experimental results show that the clock can be successfully extracted from 160Gbit/s optical time-division multiplexing (OTDM) data signal and employed for demultiplexing of 40Gbit/s tributaries.The in-band clock distribution introduces 1.5dB of power penalty with an error-free performance.     

160 Gbit/s OTDM signal transmission over 26 km photonic crystal fibre

A 160 Gbit/s (=10 Gbit/s X 16) optical time-division multiplexing (OTDM) signal is successfully transmitted over a 26 km-long photonic crystal fibre (PCF). The transmission induced signal pulse broadening is suppressed to only 0.2 ps (from 2.1 to 2.3 ps) because the fabricated PCF has low polarisation-mode dispersion (PMD) of 0.1 ps/km^1/2, and the total chromatic dispersion of the transmission line is suppressed to 0.015 ps/nm by using a dispersion-compensation fibre. The transmitted signal is demultiplexed using four-wave mixing in a 100 mlong dispersion shifted fibre, where a phase modulation-based 10 GHz pump pulse source is newly adopted.     

以光纤锁模激光器为发射源实现4×10Gbit/sOTDM信号330km传输

本文报导一个以稳定的光纤主动锁模激光器为发射源,以光电振荡器为帧时钟提取装置,以EA调制器为解复用器的4×10Gbit/s光时分复用通信实验系统。该系统成功地实现了单波长40Gbit/s数据信号在330km SMF中的色散补偿传输.     

10Gb/s NRZ码时钟信息提取电路

利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。