CONCEPT OF POWER AND SYSTEMS MODELS FOR DEVELOPING COUNTRIES

The problem of detecting nontransient faults in sequential logic circuits by random testing was analyzed by Das et al. utilizing the well-known continuous parameter Markov model. Given a sequential circuit with certain stuck faults specified, the original state table and its error version can be readily derived from analysis of the circuit under fault-free and faulty conditions, respectively. By simulating these two tables next on a computer, we can obtain the parameters of the desired Markov model. For a specified confidence degree, it is easy to derive the parameters of the model and to calculate the required lengths of the random test patterns, or the maximum testing time. This paper presents further analysis of the model and reports simulation results on VAX 11/750 system which provides some useful insights into the nature of faults in relation to random testing and the associated confidence degree.     

一种有效的边界测试点选取策略

借鉴组合逻辑电路固定型故障的诊断原理,提出一种软件边界测试点选取策略.根据RSDIMU容错软件需求规范开发出52个测试用例,同时采用边界值分析、健壮性测试等边界值测试方法设计了2组测试用例,对34个版本的RSDIMU程序和429个变异体进行了测试.实验结果表明:该方法是一种有效的边界测试点选取策略,可以克服测试的盲目性,降低测试成本,明显地提高故障覆盖程度.     

Synchrony in silicon: the gamma rhythm.

In this paper, we present a network of silicon interneurons that synchronize in the gamma frequency range (20-80 Hz). The gamma rhythm strongly influences neuronal spike timing within many brain regions, potentially playing a crucial role in computation. Yet it has largely been ignored in neuromorphic systems, which use mixed analog and digital circuits to model neurobiology in silicon. Our neurons synchronize by using shunting inhibition (conductance based) with a synaptic rise time. Synaptic rise time promotes synchrony by delaying the effect of inhibition, providing an opportune period for interneurons to spike together. Shunting inhibition, through its voltage dependence, inhibits interneurons that spike out of phase more strongly (delaying the spike further), pushing them into phase (in the next cycle). We characterize the interneuron, which consists of soma (cell body) and synapse circuits, fabricated in a 0.25-microm complementary metal-oxide-semiconductor (CMOS). Further, we show that synchronized interneurons (population of 256) spike with a period that is proportional to the synaptic rise time. We use these interneurons to entrain model excitatory principal neurons and to implement a form of object binding.     

Macro Testing: Unifying IC And Board Test

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.     

基于硅通孔绑定后三维芯片测试调度优化方案

三维芯片(3D-SIC)通过硅通孔TSV技术实现电路的垂直互连,有效提高了系统集成度和整体性能。由于三维芯片测试中,用于测试的引脚数和TSV数目以及测试时功耗的限制都对测试时间有很大的影响,拟提出一种装箱问题思想的测试方案,针对每层只有一个晶片的"单塔"结构和每层有多个晶片的"多塔"结构进行测试调度优化。该优化方案在控制测试引脚数、测试TSV数目与测试功耗的同时,能有效缩短测试时间。实验结果表明,与同类方案相比,在多种限制条件和不同结构中,都有着显著的优化结果。其中"单塔"最高优化45.28%的测试时间,"多塔"最高优化了27.78%的测试时间。     

Power transition X filling based selective Huffman encoding technique for test-data compression and Scan Power Reduction for SOCs

Due to the excessive utilization of memory, data compression is an evergreen research topic. Realizing the constant demand of compression algorithms, this article presents a compression algorithm to analyse the digital VLSI circuits for constraint optimization, such as test data volume, switching power, chip area overhead and processing speed of testing. This article proposes a new power transition X filling based selective Huffman encoding technique, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing. The performance of the proposed work is examined with the help of ISCAS benchmark circuits. Initially, the test set is occupied by using the power transition X filling technique to replace the don't care bits and the filled test set is further encoded by selective Huffman encoding technique. The experimental results show that the proposed power transition X filling based selective Huffman encoding gives effective results compared to the related data compression techniques with minimal time and memory consumption.     

驾驶员疲劳检测系统设计

以DM642为主控芯片设计了一套驾驶员疲劳检测的硬件系统,包括主控器模块、视频采集模块、视频输出模块和报警模块等相关电路;综合国内外的研究现状,确定了了疲劳状态判断的理论基础;交叉运用图像处理技术、人脸检测技术和PERCLOS疲劳检测方法,根据眼睛的疲劳特征,实时判断驾驶员的疲劳状态,进行报警,有效防止交通事故的发生;经过对系统的软硬件测试,结果表明,该方案可以有效地识别出驾驶员的疲劳状态,运行速度快、实时性好,具有较高的鲁棒性。     

基于Catalyst-200的串行DAC静态参数测试研究

文章基于大规模数模混合测试设备Catalyst-200,采用最佳拟合直线法,对串行数模转换器的测试方法进行研究,并以AD5317为例,进行其静态参数差分非线性和积分非线性的测试,通过合理设计数字pattern控制串行模数转换器的控制字和数据输入,同时对转换控制信号进行时序分析,最终得到相应的测试曲线和测试值,证明了测试方法的正确性。文章的研究成果为开展其它串行数模混合信号集成电路的测试研究奠定了基础。     

面向测试优化的片上网络映射算法

针对复杂片上系统(SoC)芯片的片上网络(NoC）映射方案未考虑测试需求的问题,提出了一种面向测试优化的NoC映射算法,兼顾了可测性的提升和映射开销的最小化。该映射方案首先依据特定的测试结构,使用划分算法进行片上系统所有IP核的测试分组,其优化目标为测试时间最短;之后,再基于分组内IP核之间的通信量,应用遗传算法实现NoC映射,其优化目标是在测试优化的基础上实现映射开销最小。通过多个ITC'02测试基准电路进行的实验结果表明:应用该方案后,测试时间平均减少12.67%;与随机任务映射相比,映射代价平均减少24.5%。     

基于扫描的低测试功耗结构设计

在集成电路设计中,面积、功耗和可测性是3个最为重要的优化指标,测试成本正随着集成电路规模的不断增大而提高,因此在设计中加入可测性设计的考虑已成为共识,基于扫描的可测性设计方法是目前应用最广泛的方法之一,加入扫描结构可以大大提高电路系统的测试性能,但同时也会给系统的面积、性能、功耗等带来一些负面影响,提出一种考虑低功耗因素的可测性设计方法,计算数据显示,与传统扫描设计方法相比,这种方法在改善系统测试功耗方面具有突出的优势。     

带时间参数的测试产生

进延测试对于高速集成电路非常重要。本文介绍一个带时间参烽的时延测试产生系统。该系统使用一个时刻逻辑值来表示一个波形,并将输入波形限制为只有唯一的一个输入在０时刻有跳变,其它输入为稳定的０或１,从而实现了波形敏化条件下的时延测试产生,与以往的不考察时间因素的时延测试产生系统相比,带时间参烽的测试产生提高了故障覆盖率,并且更接近于电路的实际。     

基于ARM9的航空相机测控系统设计与实现

性能测试是航空数码相机生产和装备过程中非常重要的一个环节,对其的使用评估有着不可替代的作用;以三星的ARM9处理器S3C2440A和Windows CE操作系统为核心,结合现代接口技术,介绍了某型航空数码相机地面检测系统总体设计思路和系统构成,重点分析了主体电路的硬件设计和Windows CE系统下相关软件的编写;通过BCD拨码器,串口电路,处理器和LED数码管组成模块模拟飞行状态输入和显示,编写相关软件完成了图像数据的格式转变和实时显示;实际使用结果显示,该检测系统运行稳定可靠,具有一定的实用性和参考价值。     

基于ARM的某型导弹数据采集系统设计

针对某型导弹装备数据采集系统体积大、可靠性低的问题,设计开发以ARM处理器S3C2440A和嵌入式实时操作系统WinCE为基础的数据采集系统,给出系统的总体实现方案,软硬件结构框图。系统由ARM最小系统,人机交互电路,通信电路,信号转换电路组成。测试结果表明,整个系统功耗低、体积小、执行速度快、可靠性高,实现了对某型导弹装备的实时数据采集、处理和显示等功能。     

CMOS电路瞬态电流测试方法研究

集成电路设计与测试是当今计算机技术研究的主要问题之一。集成电路测试技术是生产高性能集成电路和提高集成电路成品率的关键。基于固定型故障模型的测试方法已不能满足高性能集成电路,尤其是对CMOS电路的测试要求。CMOS电路的瞬态电流(IDDT)测试方法自80年代提出以来,已被工业界采用,作为高可靠芯片的测试手段。     

Accumulator-based pseudo-exhaustive two-pattern generation

In this paper, a novel scheme for the generation of pseudo-exhaustive two-pattern tests for combinational modules under test is presented. The proposed scheme utilizes an accumulator with 1’s complement adder to generate the patterns in time equal to the theoretical minimum. Since accumulators are commonly found in current, high-speed signal processing VLSI circuits, the presented scheme may prove a practical solution for the pseudo-exhaustive testing of such circuits for delay and stuck-open faults.Comparisons of the proposed scheme with previously proposed schemes for pseudo-exhaustive two-pattern testing reveals that the proposed generator compares favorably with respect to the required hardware overhead.     

气密检漏泄漏量测试系统的设计

介绍了一种基于直压检漏法和红外皂膜流量计技术设计的智能检漏泄漏量测试仪器,这种仪器兼备检漏测试和泄漏量测试的功能;通过分析可消除自然光直流干扰的皂膜检测调理电路的工作原理,简化了皂膜计的结构,并且论述了泄漏量检测原理、气路设计、硬件电路和软件设计,设计出检漏泄漏量测试为一体的高精度、便携式的检漏泄漏量测试仪器。     

Computer controlled testing of batteries

This paper describes a computer controlled testing device for experimental batteries. The hardware consists of an IBM compatible personal computer and a data acquisition and control interface with additional relay and multiplexer circuits. The software package is written in Turbo-Pascal.The system is capable of cycling several batteries simultaneously. Charging and discharging of the batteries is controlled by preset cut off voltages and preset maximum charge times. Several parameters which give information about the batteries under test are recorded. Measurements are displayed in real time on the display.The main advantages of the system are: low price, easy to modify and high accuracy and reliability of the measurements.     

Low Cost Scan Test by Test Correlation Utilization

Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.     

GSM智能测控仪的设计与实现

给出了一个基于GSM的智能测控仪的设计方案。该方案主要包括基于P89V51RD2BN高性能MCU的最小系统、TC35IGSM驱动电路、DS1302时钟电路、数据采集电路等。同时在数据处理环节，采用了模糊控制算法，提高了系统的智能性。     

基于虚拟仪器技术的电路测试和诊断系统

介绍了一个智能电路测试和诊断系统的软硬件设计。该系统基于虚拟仪器技术设计而成，由测试模块、诊断模块和使用帮助模块组成，测试模块是通过实际测量得到的电路输出信号和测试库中的参考信号进行比对来判断该电路功能的正确性，而故障诊断模块则是采用故障树的方法自顾问下地逐步定位电路中的故障点，系统还可以对单独的元件和导线进行测试和诊断。本系统利用LabWindows/CV1作为开发平台，实现了对一些常见实验电路的分析。