A global delay model for domino cmos circuits with application to transistor sizing

Domino CMOS circuits have played important roles in the design of high-speed VLSI chips such as 32-bit microprocessors and their family chips. Many researchers have worked on the characterization of the delay time and optimal design of domino CMOS circuits using circuit simulators as the main CAD tools. This paper presents a global analytical delay model for an important class of domino CMOS circuits wherein a multitude of n-channel transistors form a series connection. the new model is shown to predict the delay time from the precharging clock edge to the 0.5 V_DD output level with less than 10% error as compared to that from SPICE simulation over the entire design space. the delay model has been applied efficiently to the design automation of domino CMOS circuits modules.     

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm² the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.     

FinFET-based power-efficient,low leakage,and area-efficient DWT lifting architecture using power gating and reversible logic

For ultra-low-power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET-based lifting-based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET-based transform to reduce the dynamic power by about 30%. The proposed FinFET-based processing elements were utilized in the various blocks of the lifting-based DWT architecture. The implementation was done in 32-nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET-based circuits are efficient when compared with CMOS technology. This is due to the second-order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.     

A symmetric lattice-based wideband wide phase range digital phase shifter topology

In this paper, a novel digital phase shifter topology that achieves wideband and wide phase range is proposed. Wide frequency band operation is accomplished employing symmetrical all-pass lattice structures. Compact phase shifter size is obtained utilizing the miniaturized microwave monolithic integrated circuit (MMIC) design implementation technology. Therefore, resulting phase shifter units are suitable for various communication systems such as radar and cellular communication smart antenna arrays. This paper provides complete design equations together with design algorithm for the selected phase shift and the center frequency. Design algorithm is developed on MatLab environment. The proposed phase shifting circuit is implemented employing the commercially available 0.18-μm silicon CMOS technology. The new phase shifter topology provides 0⁰ to 360⁰ phase shift range over X-band, even beyond.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

An ATM-based intelligent optical backplane using CMOS-SEED smartpixel arrays and free-space optical interconnect modules

The architecture, smart pixel array chip design, and optical design of an intelligent free-space digital optical backplane for ATM switching are presented. The smart pixel chip uses reflective SEED (self-electrooptic effect device) optical modulators and detectors flip-chip bonded to CMOS circuitry. This chip is one of the most complex designs ever reported in this technology, and it operates at a simulated backplane clock rate of 125 MHz. The low-loss optical system employs f/4 diffractive minilenses and microlenses to interconnect clusters of smart pixels, and it is shown to allow 2060 connections per chip if 1-cm² -sized smart pixel chips are used. This gives a predicted bisection bandwidth of around 1 Tb/s across a 10-in circuit board edge for a full-sized system     

Preliminary results from an analog implementation of first‐order TDCNN dynamics

This work falls into the category of linear cellular neural network (CNN) implementations. We detail the first investigative attempt on the CMOS analog VLSI implementation of a recently proposed network formalism, which introduces time‐derivative ‘diffusion’ between CNN cells for nonseparable spatiotemporal filtering applications—the temporal‐derivative CNNs (TDCNNs). The reported circuit consists of an array of Gm‐C filters arranged in a regular pattern across space. We show that the state–space coupling between the Gm‐C‐based array elements realizes stable and linear first‐order (temporal) TDCNN dynamics. The implementation is based on linearized operational transconductance amplifiers and Class‐AB current mirrors. Measured results from the investigative prototype chip that confirms the stability and linearity of the realized TDCNN are provided. The prototype chip has been built in the AMS 0.35 µm CMOS technology and occupies a total area of 12.6 mm sq, while consuming 1.2 µW per processing cell. Copyright © 2010 John Wiley & Sons, Ltd.     

A flexible current‐mode classifier circuit and its applications

In this paper a new CMOS classifier circuit is presented, simulated, and compared with other recently introduced circuits. The proposed CMOS circuit operates in current‐mode and can classify several types of data. The architecture is designed using two threshold circuits and a subtraction circuit. Among many possible applications of the classifier circuit, template‐based pattern classification, namely template matching and character recognition with corruption, and in another direction its use as a quantizer are given. Using 0.35‐ µm AMS technology parameters, SPICE simulations as well as hard realization results for the classifier and application circuits are included; detailed Monte Carlo analyses to assess parameter mismatch effects are also performed. Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

Low-power compact tunable quenching configuration for minimizing afterpulsing in single-photon avalanche diodes

This paper unveils two efficient free running (FR) quenching circuits with the aim of reducing quenching time (QT) to minimize avalanche charge. Likewise, one circuit is compactly designed with low power consumption, suitable for single-photon avalanche diode ( SPAD) with hold-off time below 10 ns. In second circuit, tunable hold-off and reset-time are provided within a wide range without decreasing QT, which are desirable in many applications. Proper operation and circuit uncertainty is assessed by Monte Carlo analysis in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. In a bid to do a comparison between previously reported circuits and the proposed circuits, they are simulated with same SPAD model and parameters and results corroborate the proposed circuits guarantee active quenching time (AQT) of below 1 ns. Proposed circuits with current and area consumption of 0.74 μA, 32 μm² for 7-ns dead time and 16.2 μA, 93 μm² for 21-ns dead time are more efficient in terms of QT, area, and power consumption in comparison with other works.     

Recent progress on CMOS successive approximation ADCs

Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture, it achieves a very high speed conversion rate of 90 G‐sample/s with an 8‐bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10‐bit, 200 k‐sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR‐ADC circuit techniques and the achieved performances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Improvements to a Microelectronic Design and Fabrication Course

This paper presents improvements made to a complimentary metal–oxide–semiconductor (CMOS) fabrication laboratory course to increase student learning and student impact (enrollment). The three main improvements to the course discussed include: 1) use of a two-mask MOS process that significantly reduced the time students took previously to design, fabricate, and verify the electrical properties of a metal–oxide–semiconductor field-effect transistor (MOSFET) process; 2) students' use of a semicustom integrated circuit (IC) design that significantly reduced the average design and processing time of previous years; and 3) development and implementation of a system of course prerequisites, which allowed a larger number of students to enroll in the course.     

A CMOS combinational circuit-design method using mixed logicconcepts

Presented in this paper is a method which can be used for the implementation of CMOS transistor combinational circuit design using mixed logic digital design techniques. The mixed logic method presented in this paper provides a systematic way of developing minimal transistor count combinational circuits. Additionally, students find the straight forward rules associated with the mixed logic design method allows them to quickly develop CMOS combinational circuit design skills. Examples of the circuit realizations developed using mixed and positive logic design methods as well as a comparison of the design methods are presented in this paper     

Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics

Time-frequency domain signal processing of neural recordings, from high-density microelectrode arrays implanted in the cortex, is highly desired to ease the bandwidth bottleneck associated with data transfer to extra-cranial processing units. Because of its energy compactness features, discrete wavelet transform (DWT) has been shown to provide efficient data compression for neural records without compromising the information content. This paper describes an area-power minimized hardware implementation of the lifting scheme for multilevel, multichannel DWT with quantized filter coefficients and integer computation. Performance tradeoffs and key design decisions for implantable neuroprosthetics are presented. A 32-channel 4-level version of the circuit has been custom designed in 0.18-mum CMOS and occupies only 0.22 mm² area and consumes 76 muW of power, making it highly suitable for implantable neural interface applications requiring wireless data transfer.     

新型数字式高压保护装置硬件平台设计

在总结和继承微机保护装置成功经验的基础上,设计开发了运算DSP加逻辑MPU控制单元的新型硬件平台系统。该系统充分发挥了DSP运算能力强和MPU逻辑功能强、外围资源丰富等优点,且采用大容量外围存储芯片,从而保证了高压保护装置实现高速采样、实时并行计算、程序面向对象模块化编程、故障处理报告详细全程跟踪、采用复杂先进保护原理等功能,并且具有足够的硬件资源冗余度。详细介绍了该硬件平台的系统设计思想、技术特点和工作原理,最后介绍了基于此硬件平台实现高压微机线路保护的应用实例。     

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm _* 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.     

IEEE-1394b光总线扩展技术研究

本文提出一种基于IEEE-1394b协议的光总线系统实现方案。并以DSP和IEEE1394b协议芯片为基础,利用CPLD进行时序配合,完成了光总线系统总线扩展电路的硬件电路和程序设计,使光总线系统可以兼容采用多种通用通信协议的设备。在基于总线扩展电路搭建的光总线系统中,从PC端的总线系统网络拓扑图可以看出所设计的总线扩展电路可以满足应用的需求。     

An in-circuit emulator for TMS320C25

An in-circuit emulator (ICE) is a piece of indispensable equipment in developing a microprocessor-based system. Digital signal processor (DSP) chips like the TMS320 family are VLSI processors with superior 16-bit microcomputer internal architecture, and are designed to support a wide range of computation-intensive and high-speed applications. Development tools, such as full-speed emulators and software simulators for DSP chips, are either too expensive or too complicated to be used in laboratory classes for teaching purposes. This paper describes the design and implementation of a low-cost in-circuit emulator for the TMS320C25 that has all the necessary facilities for debugging hardware and software. A window-based user interface has been incorporated to allow maximum user friendliness. The emulator is now widely used by engineering students in the Chinese University of Hong Kong for experimental work and project development employing TMS320C25 DSP chips in digital filtering, speech analysis, image compression, and other applications     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.