On the universe of stable cellular neural networks

A cellular neural network (CNN) is a novel analogue circuit architecture with many desirable features. This paper extends previous stability results of CNNs to include classes of strictly sign-symmetric and acyclic templates. We show that most of the 3×3 strictly sign-symmetric templates are stable almost everywhere, with the unknown templates reduced to three classes. We also introduce template graphs and CNN graphs and utilize them to obtain results concerning stability and irreducibility of CNN templates.     

Limitations and complexity of digital hardware simulators used for large-scale analogue circuit and system dynamics

Large-scale electronic circuits and systems are considered with increasing complexity measured in terms of the number of circuit or system elements. the dynamics will be calculated by a digital prototype hardware simulator exploiting parallelism, pipelining and look-up table techniques to realize minimum solution time. Our ‘canonical’ conceptual prototype digital simulator (PDS) is given and its parts are analysed in detail, including a minimal memory realization of a multivariable non-linear mapping (look-up table). It is shown that if the increase of the complexity of the simulator does not exceed the increase of the complexity of the circuit or system to be simulated, then the simulation complexity (measured in terms of the accumulated time of basic calculation steps) will not decrease, but instead will increase. Hence there is an inherent limitation in the digital simulation of analogue operators. This result suggests at the same time that the digital method of data and signal processing has some inherent limitations, a striking example of overcoming it being the neural circuit. the speeding up of the digital hardware due to the scaling down of feature sizes in integrated circuits and the reduction of the time step due to the increase in system size are also taken into account.     

基于dsPIC30F2020的移相控制全桥变换器

介绍了dsPIC30F2020芯片及其在DC／DC变换器控制中的应用,并用该芯片作为主控制芯片设计了一个平均电流模式控制的移相控制全桥DC／DC变换器,最后比较了数字式控制DC／DC变换器与模拟电路控制的DC／DC变换器的优缺点。     

Cellular neural networks with non-linear and delay-type template elements and non-uniform grids

The cellular neural network (CNN) paradigm is a powerful framework for analogue non-linear processing arrays placed on a regular grid. In this paper we extend the current repertoire of CNN cloning template elements (atoms) by introducing additional non-linear and delay-type characteristics. In addition, architectures with non-uniform processors and neighbourhoods (grid sizes) are introduced. With this generalization, several well-known and powerful analogue array-computing structures can be interpreted as special cases of the CNN. Moreover, we show that the CNN with these generalized cloning templates has a general programmable circuit structure (a prototype machine) with analogue macros and algorithms. the relations with the cellular automaton (CA) and the systolic array (SA) are analysed. Finally, some robust stability results and the state space structure of the dynamics are presented.     

Concurrent analogue fault simulation,the equation formulation aspect

Fault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well‐established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault‐free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated. Copyright © 2004 John Wiley & Sons, Ltd.     

A uniform approach to mixed-signal circuit test

Owing to the analogue nature of many industrial processes and the increasing use of microprocessor techniques, many circuits nowadays carry mixed (digital and analogue) signals. As complexities of these circuits increase, the testability of mixed-signal circuits has become an important issue that must be dealt with by both design and test engineers. A systematic approach to study the testability of mixed-signal circuits is urgently needed, because current ad hoc methods cannot efficiently handle increasingly complex and ever-changing circuits. In this paper we develop a uniform and systematic approach to the mixed-signal circuit testability problem. The approach is based on a recently developed theory of discrete event systems. It is suitable for the following tasks: (i) checking the testability of a circuit; (ii) computing the minimum test set; (iii) finding the fault coverage; (iv) dividing a circuit into testable modules. © 1997 by John Wiley & Sons, Ltd.     

一种新型晶闸管软起动器控制电路的设计

针对目前晶闸管软起动器控制电路的缺点,提出了一种新型控制电路设计,采用模拟电路分担部分单片机工作,结合了模拟和数字电路的优点.样机试验结果表明,该设计电路结构简单,软件开发容易,使用方便,能够完成电机软起动、软停车及多种保护功能.     

PastA—the characterization of the inherent fluctuations in the fabrication process for circuit simulation

For worst-case analysis, Monte Carlo analysis, yield optimization and design centring, the variations and correlations of the device model parameters in the electrical circuit simulation are of fundamental significance. This paper describes a method for the complete characterization of the inherent fluctuations in the fabrication process for the simulation in IC design. the emphasis is placed on analogue simulation owing to the complex connections between circuit design and technology and the multitude of devices with correlated parameters; nevertheless, statistical requirements for digital simulation can be fully covered. This characterization works with all technologies whether CMOS, BiCMOS or bipolar. the prerequisites are accurate nominal device model parameters for the circuit simulation and information about fabrication statistics, e.g. process control monitor measurements. A new approach with connection coefficients for the calculation of the correlation coefficients is presented. Dependent parameters can be easily defined through a connection hierarchy. With the presented approach the variations and correlations of model parameters for simulation can be generated from estimates or measurements of the fabrication process. Based on sensitivity analysis, the variations and correlations of design objectives can be estimated. This enables the designer to do circuit analysis and optimization (limit parameters, worst-case distances) as well as Monte Carlo analysis.     

Design of stable two-dimensional analogue and digital filters with applications in image processing

A method is proposed for the frequency domain design of linear two-dimensional analogue and digital filters with guaranteed stability. The technique used is based on the result that the numerator and the denominator of the input immittance of a two-variable network (which is passive and lossy) are strictly Hurwitz polynomials. One of these strictly Hurwitz polynomials is assigned to the denominator of a two-variable analogue transfer function and the network elements are then used as the variables of optimization thereby guaranteeing the stability of the analogue transfer function. The transfer function of the corresponding two-dimensional discrete (digital) filter is obtained from the analogue transfer function by the bilinear transformation. Examples illustrating the versatility of the technique in designing 2D digital filters of arbitrary order approximating a given magnitude and group delay response are presented. These filters are used to process a simple binary image. The results obtained demonstrate the importance of linear phase in image processing applications. The method presented here can be extended to the design of stable m-dimensional analogue and digital filters.     

An experiment on the layout and grounding of power distributionwires in a printed circuit board

An experiment has been designed with the aim to enhance the students' understanding in the topic of conducted electromagnetic interference (EMI). A printed circuit board (PCB) is developed with a motor driver circuit, a digital clock generator, and a sinewave oscillator on board. The digital and analog signals are monitored using an oscilloscope to study the interference effects. The circuit module is duplicated with a different grounding system. A separate ground system proves to be very effective in reducing the conducted EMI. Further noise reduction can be achieved using decoupling capacitors or L-network filters. The effectiveness depends on the location where these additional components are applied. The effect of ground loop is also studied in the experiment     

Automation of the ic layout of continuous-time transconductance-capacitor filters

To exploit the increased circuit density available in current technologies for continuous-time (c-t) systems, it is proposed to extend the range of analogue design automation to the larger c-t subsystems, specifically filters, commonly found in communications, mass storage devices and other interfaces to real-world signals. the synthesis is based on LC ladder simulation using only transconductances and grounded capacitors (TGC). the method retains many of the characteristics of digital design automation and therefore allows a direct mapping of these techniques. the TGC approach is shown to require a minimum of component types which are ideally suited to integration in MOS, bipolar or GaAs technologies. A simple example for the automation of c-t filter designs as well as results of CMOS c-t filters are included to demonstrate the viability of this approach. Related and equally important areas addressed are tuning, compensation for parasitics and scaling.     

Adaptive switched capacitor biquadratic filter with high-frequency applications

This paper considers the design of an adaptive biquadratic switched capacitor (SC) filter. It uses a low-sensitivity SC integrator, a gain stage and four-quadrant analogue multipliers (4-QAMs). The resulting circuit exhibits reduced sensitivity to op amp non-idealities (DC offset, finite op amp gain and bandwidth) associated with analogue adaptive filters. The techniques used are specific to high-precision and high-frequency operation. Test results obtained from a prototype circuit verify the viability of the proposed architecture.     

基于ATmega16的智能数控高压直流电源的设计

为满足高压电源小型化、智能化的要求,介绍了以ATmega16单片机为核心的智能数控高压直流电源的软硬件实现方法。采用软件仿真和硬件电路调试相结合的方法,对模拟电路部分的主要功能模块进行了详细说明,重点讨论了控制电路中高频PWM方波产生的原理、驱动方案以及输出电压/电流信号的采样反馈,并简要叙述了其他控制电路的设计思路。试验证明:该电源完全可以于核辐射探测仪器等领域,且具有密码保护、集成度高、数字控制、人机界面友好、输出电压持续可调、自动过压过流保护等优点。     

一种新型双PWM三电平变频调速系统

以双PWM三电平矿井提升机磁链定向调速系统为研究对象,提出了一种混合箝位式双PWM三电平变换器的电路拓扑,详细介绍了该变换器的工作原理,设计了基于数字信号处理器(DSP)和复杂可编程逻辑器件(CPLD)的控制电路和主电路.实验证明,该变频调速系统具有高功率闪数、可用低耐压开关管串联、四象限运行及良好的动态性能等优点,比较通用于大功率矿井提升机的变频调速场合.     

LSI Based Three-Phase Thyristor Firing Circuit

A three-phase thyristor firing circuit has been developed to meet the needs of the static power conversion industry. The circuit consists of a three-phase phase-locked loop with digital countdown and phase division to provide delayed equidistant thyristor firing pulses. The delay angle is unaffected by frequency or phase rotation. The major portion of the circuit is implemented in a low-cost 22-pin large-scale integrated (LSI) circuit.     

Stability Analysis of Thyristor Current Controllers

The operational stability areas of proportional-integral (PI) controllers implemented in analogue, analogue with discrete sampling, and digital form have been theoretically investigated. Whereas in the continuous-data control system, stability may be-maintained by compensating any increase of proportional gain Kp with integral gain, Ki, the discretized system tends to become unstable if either Kp or Ki is increased. A new stability area is shown to exist for a discrete-sampled system with puire integral control and large gain (which is unstable when implemented in analogue form). This result is confirmed experimentally.     

基于ISP技术的远程升级智能仪表的设计

本文使用可编程技术、嵌入式微控制器及网络技术,介绍远程升级智能仪表的设计.该设计主要采用W78E516单片机、在系统电可编程模拟电路EPAC及数字电路EPDC构建智能仪表的升级硬件平台,详述了智能仪表实现远程硬件功能重构和系统升级的工作原理.重点说明了嵌入式智能仪表硬件和软件的设计方法,对系统远程升级的可靠性和保密性进行了论述.最后,对系统硬件和软件进行了测试,实验证明系统性能稳定、操作灵活,能可靠实现远程自动升级.     

静电放电损伤自修复数字电路模型的建立与优化

为了使数字电路在产生故障失效后实现功能自动恢复,提高电路可靠性,基于演化硬件(EHW)原理建立了自修复数字电路模型,该模型主要包括微处理器和重配置电路2个部分。利用自修复数字电路模型实现无刷直流电机控制系统中的换相电路,并对换相电路进行了故障注入修复实验。深入分析了自修复数字电路模型对电路演化修复的影响,通过引入关键函数对自修复数字电路模型进行了改进。实验结果表明,当注入故障单元数小于总单元数的50%时,改进后的自修复数字电路模型修复率达到100%。因此,该模型能够对部分故障进行成功修复,改进的自修复数字电路模型降低了电路生成时间,提高了电路修复概率和速度。     

微机控制的电磁继电器动作时间及抖动时间的自动检测

介绍了一种由微机控制的对ＤＬ、ＤＹ－２０Ｃ系列电流、电压电磁继电器动作时间及抖动时间自动检测的方法。它综合应用了模拟、数字电子技术及计算机技术。由于采用了ＳＴＡ、ＳＴＢ控制电路，实现了动作时间测量的规范化．抖动时间检测电路的设计，解决了多年来国内对出厂电流、电压电磁继电器抖动时间无法检测的难题。     

SPWM数字化自然采样法的理论及应用研究

该文提出一种基于CPLD(复杂可编程逻辑器件)、由全数字化方法实现自然采样法的SPWM(正弦脉宽调制)新方案。该方案同时具有数字电路稳定可靠便于集成、微处理器可以重复编程、以及自然采样法响应快精度高等优点。对正弦调制信号us(t)的数字化处理，会引起SPWM输出脉冲宽度的误差。当us(t)斜率为正时输出负脉冲变宽；us(t)的斜率为负时输出正脉冲变宽：这相当于在输出基波上附加了一个齐次谐波分量。SPWM数字化自然采样法存在脉冲竞争现象。研究表明最大误差脉冲宽度和竞争脉冲宽度均与模数转换的采样周期和调制深度成正比，与载波比成反比；竞争脉冲的个数由us(t)的斜率决定。给出了消除竞争脉冲的方法。在一台4kVA单相SPWM电压型并联四重化逆变器上取得了满意的实验结果。