Single transistor technique for interface trap density measurement in irradiated MOS devices

The effect of interface trap charge variation during measurement of the MOSFET current–voltage characteristic has been examined. Taking into account this effect, an interface trap density extraction technique is proposed. The transconductance degradation in this technique is caused not only by channel mobility decrease, but also by I_d(V_g) curve distortion due to interface trapped charge variation during measurement. The analytical and numerical models for the effect are developed. The experimental data on channel mobility and interface trap density vs total dose are shown.     

Determination of interface trap capture cross sections usingthree-level charge pumping

A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO₂ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I_cp to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET     

Reversible and irreversible interface trap centres generated at high electric fields in MOS structures

In this work, we present results of the study of interface trap generation processes at the Si–SiO₂ interface in MOSFET structures caused by high oxide field stress. Changes in areal density and energy distribution in the Si band gap of the interface traps were monitored using the II-level conventional charge pumping technique. The generated interface traps were divided into two types: reversible and irreversible in relation to their discharge by low field electron injection. A broad presentation of changes in density and energy distribution of the interface traps was included. The threshold value of oxide field for interface trap generation was obtained.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Characterization of oxide traps in 0.15 μm MOSFETs using random telegraph signals

Random telegraph signals (RTS) have been used to characterize oxide traps of W×L=0.97×0.15 μm² medium-doped drain n-MOSFETs. RTS have been measured in the linear and saturation regions of operation, both in forward and reverse modes where the drain and source are reversed. The contribution of mobility fluctuations as well as number fluctuations to the amplitude of RTS has been investigated. The scattering coefficient due to screened Coulomb scattering effect is computed from the measured data as a function of channel carrier density. The depth of the position of the trap in the oxide from Si–SiO₂ interface is calculated utilizing the dependence of the emission and capture times on the gate voltage. In addition, the position of the trap along the channel with respect to the source is obtained using the difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes. Knowing the location of the trap in the oxide and along the channel, the energy associated with the trap can be extracted accurately from the data. This technique allows one to evaluate the trap energy at the point where the trap is located without any assumptions about the location of the trap or the need for variable temperature measurements. The probed trap was found to be an acceptor type center (repulsive for an n-MOSFET) located at about 27 Å deep the oxide, half-way between drain and source with an energy of E_Cox−E_T=3.04 eV, slightly above the conduction band edge.     

低电压静电放电脉冲引起的界面损伤(英文)

It was found that the interface between gate oxide and substrate could be damaged by the low voltage electrostatic discharge pulse applied to the gate and source terminals of a MOSFET, even though the amplitude of the pulse was lower than the value causing catastrophic failure of the MOSFET.As the result of the damage, the interface trap density Nit increased-ashigh as one order. Compared to those traps far from the middle of the energy gap Ei, the traps near Ei was found to be increased more rapidly with the increasing of the pulse number. After the discharge pulse was over, the Nit value of the sample tended to decrease automatically. The time constant of the recovery is related to the pulse amplitude. The generation of the interface trap reduced the subthreshold transconductor of MOSFET. Discharge pulse can also induce a positive or negative charge in the gate oxide.     

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N₂O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N₂O nitridation piles up in the oxide at the Si–SiO₂ interface regardless of nitridation time. The results obtained show improved breakdown field (E_bd), and charge-to-breakdown (Q_bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density (D_it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.     

A new I–V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect

We present a new I–V model for a long-channel surrounding-gate (SG) metal–oxide–semiconductor field-effect transistor (MOSFET). SG MOSFET is a strong candidate for next generation nanoscale devices due to a high electrostatic channel control, which in turn substantially reduces the short-channel effect. The new model takes into account quantum mechanical (QM) effects in the SG MOSFET using a double triangular QM well model in the strong inversion regime. In contrast with the old model, we consider the V _g dependence of the QM effect. New model yields excellent agreement with 2-D numerical simulation results for various radii and gate oxide thicknesses of the SG MOSFET.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义 ,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布 .发现这两种方法提取的界面陷阱密度的能量分布是自洽的 ,同时也与文献报道的 DCIV等方法的结果是一致的 .与其它的提取方法相比 ,采用弛豫谱技术的这两种方法更加简单和方便 .     

利用弛豫谱技术对界面陷阱密度和其能量分布的研究

基于界面陷阱的定义,通过分别对亚阈值摆幅漂移和亚阈区栅电压漂移采用弛豫谱技术有效地提取了1.9nm MOS结构中的界面陷阱密度和它的能量分布.发现这两种方法提取的界面陷阱密度的能量分布是自洽的,同时也与文献报道的DCIV等方法的结果是一致的.与其它的提取方法相比,采用弛豫谱技术的这两种方法更加简单和方便.     

Energy level of minority carrier trap centers induced by light illumination in B-doped Cz-Si solar cells

The conversion efficiency of boron (B)-doped Czochralski silicon (Cz-Si) solar cells decreased by light illumination or minority carrier injection. Defects are induced by illumination and they act as trap centers, shorten the minority carrier (electron) lifetime. The energy level of this minority carrier trap center was determined by analyzing the open-circuit voltage (V_OC) changes as a function of substrate temperature. When substrate temperature is low, all electrons which are captured by the trap centers recombine with holes and they do not contribute to the generation of electric power. However, as the substrate temperature is increasing, some of the captured electrons are thermally excited to the conduction band before recombination. Hence, the lifetime of minority carriers are improved and V_OC is recovered. Based on this result, the energy level of trap center induced by light illumination is estimated to be 0.26 eV, which corresponds to the boron–oxygen-related defect (E_C-0.26 eV).     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Phosphorous passivation of the SiO2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO₂/4H–SiC interface. Annealing in a P₂O₅ ambient converts the SiO₂ layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm²/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.     

Backgatting effect in GaAs FETs with a channel–semi-insulating substrate boundaryAhmed Chaouki Megherbi a,*, Said Benramache b, Abderrazak Guettaf a

This study focuses on modeling the effects of deep hole traps, mainly the effect of the substrate（backgating effect） in a GaAs transistor MESFT. This effect is explained by the existence, at the interface, of a space charge zone. Any modulation in this area leads to response levels trapping the holes therein to the operating temperature. We subsequently developed a model treating the channel substrate interface as an N–P junction, allowing us to deduce the time dependence of the component parameters of the total resistance R ds, the pinch-off voltage V P, channel resistance, fully open R co and the parasitic series resistance R S to bind the effect trap holes H1and H0. When compared with the experimental results, the values of the R DS（t S/ model for both traps show that there is an agreement between theory and experiment; it has inferred parameter traps, namely the density and the time constant of the trap. This means that a space charge region exists at the channel–substrate interface and that the properties can be approximated to an N–P junction.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability

The properties of the so-called time dependent dielectric breakdown (TDDB) of silicon dioxide-based gate dielectric for microelectronics technology have been investigated and reviewed. Experimental data covering a wide range of oxide thickness, stress voltage, temperature, and for the two bias polarities were gathered using structures with a wide range of gate oxide areas, and over very long stress times. Thickness dependence of oxide breakdown was shown to be in excellent agreement with statistical models founded in the percolation theory which explain the drastic reduction of the time-to-breakdown with decreasing oxide thickness. The voltage dependence of time-to-breakdown was found to follow a power-law behavior rather than an exponential law as commonly assumed. Our investigation on the inter-relationship between voltage and temperature dependencies of oxide breakdown reveals that a strong temperature activation with non-Arrhenius behavior is consistent with the power-law voltage dependence. The power-law voltage dependence in combination with strong temperature activation provides the most important reliability relief in compensation for the strong decrease of time-to-breakdown resulting from the reduction of the oxide thickness.Using the maximum energy of injected electrons at the anode interface as breakdown variable, we have resolved the polarity gap of time- and charge-to-breakdown (T_BD and Q_BD), confirming that the fluency and the electron energy at anode interface are the fundamental quantities controlling oxide breakdown. Combining this large database with a recently proposed cell-based analytical version of the percolation model, we extract the defect generation efficiency responsible for breakdown. Following a review of different breakdown mechanisms and models, we discuss how the release of hydrogen through the coupling between vibrational and electronic degrees of freedom can explain the power-law dependence of defect generation efficiency. On the basis of these results, a unified and global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits. In this regard, it is concluded that SiO₂-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable for the 50 nm technology node.     

Interface characterization of fully depleted SOI MOSFETs by thedynamic transconductance technique

The dynamic transconductance technique of MOSFET interface characterization is adapted to fully depleted silicon-on-insulator (SOI) transistors and is used to measure the interface-state density energy profiles in several SIMOX (separation by implanted oxygen) transistors. By making measurements first with the current flowing through the channel under measurement and then through the opposite channel, much of the energy gap (from accumulation to well into weak inversion) can be probed. Remarkably high sensitivity is achieved by utilizing the imaginary part of the dynamic transconductance. Measured interface trap densities were in the region of ~10¹⁰-10¹¹ eV^-1-cm^-2     

Electrical reliability aspects of through the gate implanted MOS structures with thin oxides

The effect of through the gate implantation (TGI) on MOS devices with oxide thicknesses of 3.3, 4.0, and 20 nm is studied, utilizing constant voltage stress tests and a substrate hot electron (SHE) injection technique. For 3.3 and 4.0 nm thick oxides, a dependence of time to breakdown on TGI dose is detected which, for 3.3 nm samples, diminishes with increasing test voltage. SHE injection measurements show a TGI induced increase in intrinsic electron trap density and also an increase in trap generation rate during sample stressing. A change of electron trap generation dynamics seems to be the main cause for oxide weakening due to TGI.