Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

High frequency active-R filters

Limitations on active-R filter pole displacements are studied. the maximum magnitude of the natural frequencies is presented as a function of the op. amp. GB. Structures to realized biqads with two op. amps. and a predistortion technique, to take into account the amplifier's high frequency pole, are proposed. Experimental results are presented which confirm the theory.     

Existence and uniqueness of solutions for DC networks containing non‐linear ideal op amps

In this paper we are concerned with networks obtained by connecting independent sources, linear resistors and non‐linear ideal op amps. A necessary and sufficient condition for the existence and uniqueness of solutions for every positive output saturation voltage of the op amps and every value of the independent sources is found. Copyright © 2001 John Wiley & Sons, Ltd.     

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.     

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

Frequency compensation of a multistage operational amplifier (op‐amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op‐amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two‐stage and three‐stage op‐amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well‐known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed‐loop poles and zeros of the op‐amp. Intuitive graphical design procedures for two‐stage and three‐stage op‐amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three‐stage op‐amp in a standard 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. With a load capacitance of 500 pF, post‐layout simulations show that the op‐amp achieves a low‐frequency gain of 144 dB, a phase margin of 58^°, and a unity‐gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8‐V supply voltage. Comparisons with the published amplifiers show that our op‐amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.     

Active RC impedances revisited

The aim of this paper is to review the synthesis, analysis and design of active RC impedances. First of all, major gaps in this classical research topic are identified. Second, a synthesis procedure is outlined to generate op-amp-based circuits which can simulate several classes of impedances of practical interest. From the resulting classification, all circuits are analysed from a perspective wider than those normally used in previous works, yielding some new interesting design conditions. A method is suggested to convert ladder passive prototypes containing either grounded inductors or FDNRs into MOSFET-C equivalent circuits using some of the new structures obtained. Finally, the use of current feedback amplifiers instead of op amps is considered. Experimental results corroborating all our theoretical predictions are incorporated in the work. © 1997 John Wiley & Sons, Ltd.     

Non-linear op-amp circuits: Existence and uniqueness of solution by inspection

Even simple circuits containing only one op amp and linear resistors can have multiple d.c. operating points. Using a realistic non-linear d.c. op-amp model which includes the saturation characteristics, this paper gives the necessary and sufficient conditions for an arbitrary op-amp circuit (containing op amps, linear resistors, strictly-increasing non-linear resistors and independent sources) to have a unique solution for all values of circuit parameters. These conditions are remarkable because they are couched strictly in topological terms. For many op-amp circuits (e.g. those containing only one op amp), the necessary and sufficient conditions can be checked by inspection.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

Sinusoidal oscillators with explicit current output employing current‐feedback op‐amps

Employing a state‐variable synthesis, a number of new current‐mode oscillators with explicit current output have been derived, which can be practically implemented from commercially available current‐feedback op‐amps (CFOA). The workability of the proposed structures has been confirmed by experimental results using AD844‐type CFOAs and some sample results have been presented. Copyright © 2008 John Wiley & Sons, Ltd.     

Circuit macromodels and large-signal behaviour of fet-input operational amplifiers

The origin of the slew rate asymmetry found experimentally in FET-input LF355 op amps is analysed in order to explain why macromodels based on a strict build-up technique can fail when used to simulate the behaviour of amplifiers driven by out-of-band large voltage signals. These simulations may be very important in predicting the effects of electromagnetic interferences conveyed to the circuit input port. Other performances of op amp macromodels designed either by build-up techniques or by simplification/build-up techniques are also compared and discussed.     

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

A scheme to achieve simultaneously extremely high slew‐rate improvement and avoiding open‐loop gain degradation in one‐stage super class AB op‐amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high‐output current enhancement factors at the expense of degrading the open‐loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew‐rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180‐nm complementary metal‐oxide semiconductor technology with open‐loop gain of 67 dB, a factor 2 improvement in GBW , and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley & Sons, Ltd.     

A configuration for realizing floating,linear, voltage‐controlled resistance,inductance and FDNC elements

A configuration using current feedback amplifiers has been presented, which is capable of realizing linear, positive/negative voltage‐controlled resistance, voltage‐controlled inductance and voltage‐controlled frequency‐dependent negative conductance in floating form (and thereby, also in grounded form) from the same structure. The workability of the proposed configuration has been demonstrated by hardware implementation results using AD 844‐type current feedback op‐amps (CFOAs) and BFW‐11‐type JFETs and the workability in high‐frequency range has been demonstrated by SPICE simulation using CMOS CFOAs. Copyright © 2008 John Wiley & Sons, Ltd.     

Cellular neural networks: Theory and circuit design

Cellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology. In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary-valued. A highly efficient CMOS-compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.     

The Parametric Yield Enhancement of Integrated Circuits

Even where a satisfactory circuit design has been achieved, it is often the case that, owing to variations in the manufacturing process, some of the samples of a mass-produced circuit will violate the specifications on performance so that the manufacturing yield is less than 100%. Such an undesirable effect can, however, be minimized or even eliminated by redesign of the circuit to the extent of changing parameter values while retaining the original circuit topology. For discrete component circuits algorithms are available to achieve such redesign. the special characteristics of integrated circuits, however, are such that these methods are unsuitable as they stand. Two new algorithms for handling the yield enhancement of integrated circuits are described and their successful application is illustrated in the context of two-stage CMOS op amps.     

A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high-performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a V/I converter, an ac/dc converter, an AM radio receiver, a digitally controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; results show that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level.     

An accurate reference-generating circuit for successive approximation current mode A/D converters

As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current mode signal-processing techniques will surely become increasingly important and attractive. This paper presents the design of a reference-generating (RG) circuit which employs a current mode divide-by-two circuit. Current dividers are usually implemented by using resistor networks or weighted transistors. the division accuracy of such solutions is limited by resistor or transistor mismatch. In this study the proposed divide-by-two circuit does not rely on well-matched components and high-gain op amps to achieve high accuracy. This paper also addresses the relationship among the operation and accuracy of the division process, the transistor mismatch and the resolution of a converter which employs the RG circuit. the proposed RG circuit can be implemented not only for medium-speed successive approximation current mode A/D converters but also for A/D converter arrays achieving a high conversion rate.     

The (p+q)-port transformer

Two approaches for realizing a (p+q)-port transformer using operational amplifiers are presented. Unlike iron-core transformers, our realization is valid from d.c. to a relatively high frequency limited only by the op amp's frequency response. The stability and limitation of the two approaches are analysed and compared. Examples are given to illustrate two unique and indispensible applications of the (p+q)-port transformer: Synthesis of non-linear n-ports and non-linear programming.     

On robust H∞ filtering of uncertain Markovian jump time‐delay systems

This paper is concerned with the problems of stability analysis, H_∞ performance analysis, and robust H_∞ filter design for uncertain Markovian jump linear systems with time‐varying delays. The purpose is to improve the existing results on these problems. Firstly, a new delay‐dependent stability criterion is obtained on the basis of a novel mode‐dependent Lyapunov functional. Secondly, a new delay‐dependent bounded real lemma (BRL) is derived. It is shown that the presented stability criterion and the BRL are less conservative than the existing ones in the literature. Thirdly, with the new BRL, delay‐dependent conditions for the solvability of the addressed H_∞ filtering problem are given. All the results obtained in this paper are expressed by means of strict linear matrix inequalities. Three numerical examples are provided to demonstrate the utility of the proposed methods. Copyright © 2011 John Wiley & Sons, Ltd.     

Analysis and design of voltage‐controlled current sources for a grounded load

The paper presents the structure and the principle of operation of the ‘improved’ Howland current pumps (or voltage‐controlled current sources (VCCSs) for a grounded load). In particular, under review is the VCCS employing power operational amplifier (op amp) and the VCCS using low power op amp and an additional power transistor, extending working dynamic range. On the basis of analysis of the operational principle, the equations for transfer functions of both circuits and formulas for the related dynamic electrical parameters are obtained. Moreover, using these formulas, a design procedure is developed, and recommendations for simulation modelling are given. The efficiency of the proposed procedure is verified by simulation modelling and experimental testing of sample electronic circuits of VCCSs. Copyright © 2013 John Wiley & Sons, Ltd.