Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Influence of the metal electrode on the characteristics of thermal Ta2O5 capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta₂O₅ capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta₂O₅ thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta₂O₅ during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta₂O₅, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta₂O₅ capacitors with a good quality: the current density <7 × 10⁻¹⁰ A/cm² at 1 V (0.7 MV/cm, 15 nm thick Ta₂O₅). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta₂O₅ as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta₂O₅, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.     

Polyimide/Ta2O5/polyimide antiresonantreflecting optical waveguides

A novel antiresonant reflecting optical waveguide (ARROW) fabricated using both the organic and dielectric thin film technologies is presented for the first time. The ARROW consisted of the fluorinated polyimide and tantalum pentoxide (Ta₂O₅) hybrid layers deposited on a Si substrate. For TE polarized light, the propagation loss of the waveguide as low as 0.8 dB/cm is obtained at 632.8 nm. The propagation loss for TM polarized light is 2.7 dB/cm. Some design considerations of the hybrid ARROW are also discussed in this work     

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

Hybrid polyimide/Ta2O5/polyimide antiresonantreflecting optical waveguides

A hybrid polyimide/Ta₂O₅/polyimide antiresonant reflecting optical waveguide (ARROW) is presented. The ARROW consists of fluorinated polyimide and tantalum pentoxide hybrid layers deposited on Si substrates. The propagation losses of the device are 0.6 and 2.6 dB/cm at 1.3 μm for TE and TM polarised lights, respectively     

Metal gates and gate-deposition-induced defects in Ta2O5 stack capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of Ta₂O₅ stack capacitors has been investigated. The leakage currents, breakdown fields, mechanism of conductivity and dielectric constant are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode-deposition-process-induced defects acting as electrically active centers. During deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W. The sputtered W top electrode is a good candidate as a gate of storage capacitors in DRAMs, but sputtering technique is less suitable for deposition of TiN due to the introduction of radiation defects causing deterioration of leakage current. Although some reaction between Al and Ta₂O₅ occurs, the resulting electrical properties of the capacitors are still acceptable.     

Structural and optical properties on thulium-doped LHPG-grown Ta2O5 fibres

Structural, spectroscopic and dielectric properties of thulium-doped laser-heated pedestal Ta₂O₅ as-grown fibres were studied. Undoped samples grow preferentially with a single crystalline monoclinic structure. The fibre with the lowest thulium content (0.1 at%) also shows predominantly a monoclinic phase and no intra-4f¹² Tm³⁺ recombination was observed. For sample with the highest thulium amount (1.0 at%), the appearance of a dominant triclinic phase as well as intraionic optical activation was observed. The dependence of photoluminescence on excitation energy allows identification of different site locations of Tm³⁺ ions in the lattice. The absence of recombination between the first and the ground-state multiplets as well as the temperature dependence of the observed transitions was justified by an efficient energy transfer between the Tm³⁺ ions. Microwave dielectric properties were investigated using the small perturbation theory. At a frequency of 5 GHz, the undoped material exhibits a dielectric permittivity of 21 and for thulium-doped Ta₂O₅ samples it decreases to 18 for the highest doping concentration. Nevertheless, the dielectric losses maintain a very low value.     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Conduction mechanisms in Ta2O5 stack in response to rapid thermal annealing

The influence of the rapid thermal annealing (RTA) in vacuum at 1000 °C on the leakage current characteristics and conduction mechanisms in thermal Ta₂O₅ (7-40 nm) on Si has been studied. It was established that the effect of RTA depends on both the initial parameters of the films (defined by the oxidation temperature and film thickness) and annealing time (15-60 s). The RTA tends to change the distribution and the density of the traps in stack, and this reflects on the dielectric and leakage properties. The thinner the film and the poorer the oxidation, the more susceptible the layer to heating. The short (15 s) annealing is effective in improving the leakage characteristics of poorly oxidized samples. The RTA effect, however, is rather deleterious than beneficial, for the thinner layers with good oxygen stoichiometry. RTA modifies the conduction mechanism of Ta₂O₅ films only in the high-field region. The annealing time has strong impact on the appearance of a certain type of reactions upon annealing resulting to variation of the ratio between donors and traps into Ta₂O₅, causing different degree of compensation, and consequently to domination of one of the two mechanisms at high fields (Schottky emission or Poole-Frenkel effect). Trends associated with simultaneous action of annealing and generation of traps during RTA processing, and respectively the domination of one of them, are discussed.     

Lightly Al-doped Ta2O5: Electrical properties and mechanisms of conductivity

Lightly Al-doped Ta₂O₅ films (10;15 nm) obtained by rf sputtering have been studied with respect to their dielectric and electrical properties. The formed metal-high-k dielectric-semiconductor capacitors have been characterized by capacitance-voltage and temperature-dependent current-voltage characteristics. It was established that the introduction of small amount (5 at.%) Al into the matrix of Ta₂O₅ improves dielectric constant, introduces negative oxide charge, suppresses deep oxygen-vacancy centers in Ta₂O₅ but creates shallow traps and changes the dominant conduction mechanism in the stacks. The doping produces more leaky films at room temperature and lower current at high temperature as compared to the case of pure Ta₂O₅. It is concluded that the strong contribution of tunneling processes through shallow traps in the conductivity of doped films could explain the observed current degradation at room temperature and its improved temperature stability at high temperatures. The energy levels of the traps responsible for the current transport are estimated.     

Challenges of Ta2O5 as high-k dielectric for nanoscale DRAMs

The present status, successes, challenges and future of Ta₂O₅, and mixed Ta₂O₅-based high-k layers as active component in storage capacitors of nanoscale DRAMs are discussed. The engineering of new Ta₂O₅-based dielectrics (doped Ta₂O₅ and multicomponent Ta₂O₅-based high-k dielectrics) as well as of metal/high-k interface in MIM capacitor configuration are identified as critical factors for further reduction of EOT value below 1 nm.     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

GaAs metal insulator field effect transistors with excellentintrinsic transconductance and stable drain currents using (NH4)2Sx chemical treatment

Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si₃N₄) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH₄)₂S_x. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D_it) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si ₃N₄ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 Å. Stability of the drain currents in these devices is demonstrated to be excellent     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.