High refresh rate and low power consumption AMOLED panel using top‐gate n‐oxide and p‐LTPS TFTs

A pixel circuit and a gate driver on array for light‐emitting display are presented. By simultaneously utilizing top‐gate n‐type oxide and p‐type low‐temperature polycrystalline silicon (LTPS) thin‐film transistors (TFTs), the circuits provide high refresh rate and low power consumption. An active‐matrix LED (AMOLED) panel with proposed circuits is fabricated, and driving at various refresh rate ranging from 1 to 120 Hz could be achieved.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Design of high speed gate driver employing IZO TFTs

This paper presents a new bi-side gate driver integrated by indium-zinc-oxide thin film transistors (IZO TFTs). Our optimized operate method can achieve high speed performance by employing a lower duty ratio (25%) CK2 with its pulse located in the middle of the pulse of CK2L to fully use the bootstrapped high voltage of node Q. In addition, the size of devices is optimized by calculation and simulation, and the function of the proposed gate driver is predicted by the circuit simulation. Furthermore, the proposed gate driver with 20 stages is fabricated by the IZO TFTs process. It is shown that a 2.6 μs width pulse with good noise-suppressed characteristic can be successfully output at the condition of R_load = 6 kΩ and C_load = 150 pF. The power consumption of the proposed gate driver with 20 stages is measured as 1 mW. Hence, the proposed gate driver may be applied to the display of 4K resolution (4096 × 2160) at a frame rate of 120 Hz. Moreover, there is a good stability for the proposed gate driver under 48 h operation.     

Novel 120‐Hz TFT‐LCD motion‐blur‐reduction technology with integrated motion‐compensated frame‐interpolation timing controller

Abstract— Samsung has developed a high‐resolution full‐HD (1920 × 1080) 120‐Hz LCD‐TV panel using a novel pixel structure and a motion‐compensated frame‐interpolation (McFi) single‐chip solution. Our latest work includes launch of a 70‐in. full‐HD panel, the world's largest LCD TV in mass production, with a 120‐Hz frame rate. A serious problem involving the charging time margin has been completely overcome through the use of a new alternative 1G‐2D pixel structure and a new driving scheme. Compared with conventional dot‐inversion driving, our new dot‐inversion method, which is a spatial averaging technique, can save power because the column drivers are operated using vertical inversion driving. In addition, McFi, which merges individual ME/MC and timing‐controller (TCON) ICs and memories, has been developed and applied in a mass‐production product for the first time ever. The McFi solution provides 120‐Hz driving with the lowest possible system cost. Motion‐picture response time (MPRT) has been reduced from 1 5 to 8 msec. Moreover, for the case of 24‐Hz film source mode, motion judder has been completely eliminated. As a result, a lineup consisting of 40‐, 46‐, 52‐, 70‐, and 82‐in. LCD‐TV panels with high quality and manufacturability has been made possible.     

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

We present a qHD (960 × 540 with three sub‐pixels) top‐emitting active‐matrix organic light‐emitting diode display with a 340‐ppi resolution using a self‐aligned IGZO thin‐film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven‐layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low‐temperature polycrystalline silicon. By using an IGZO thin‐film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low‐refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.     

Design of low power,high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical,logical and telecommunication circuit and system application

In this work the design of 4 bit binary to Gray code converter circuit with 8 × 4 barrel shifter has been carried out. The circuit has been designed using metal oxide semiconductor (MOS) transistor. The verification of the functionality of the circuits has been performed using Tanner-SPICE software. Power consumption and speed are the major design metrics for very large scale integrated circuit. In this work the average power consumption and gate delay analysis of 4 bit binary to Gray converter with 8 × 4 barrel shifter has been carried out using nano dimensional MOS transistor having channel length of 150 nm. Power consumption, delay analysis has been carried out for different set of supply voltage. It has been observed that power consumption of the 4 bit binary to Gray converter with 8 × 4 barrel shifter has been reduced by reducing the power supply voltage V_DD. The power consumption and delay offers by the circuit is very less. At 1 V V_DD, power consumption and delay are 0.15 μW and 52.7 ps respectively. Therefore the circuit is suited for low power and high speed application in the area of arithmetical, logical and telecommunication.

     

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

An intra‐panel interface addressing all of the high‐speed, low‐power, and low‐electromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4‐Gbps data‐rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power‐saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin‐film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65‐nm and 180‐nm complementary metal‐oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band‐20 and GSM 850 bands. The proposed power‐saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced‐voltage differential signaling interface circuit.     

Evaluation of single‐, pre‐emphasis,and dual‐driving methods in large‐sized TFT‐LCDs

Abstract— As the panel size and the frame frequency of TFT‐LCDs increases, driving issues become much more important for larger‐sized and higher‐resolution TFT‐LCDs. In our previous paper, the pre‐emphasis driving method was proposed to shorten the driving time of the data line with heavy loads of the large‐sized TFT‐LCDs. This paper proposes a simulation model based on the evaluation results of the developed pre‐emphasis source driver, and the issues of driving the data line with heavy loads are reviewed. The single‐, pre‐emphasis, and dual‐driving methods are compared in terms of their driving time and power consumption for large‐sized TFT‐LCDs with various resistances and capacitances of the data lines. At a panel load of 250‐pF capacitance and 15‐kΩ resistance in full‐HD resolution, the pre‐emphasis driving can reduce the pixel driving time to 66% with a 54% increase in the analog power consumption.     

A reduced‐voltage differential signaling (RVDS) interface for chip‐on‐glass TFT‐LCD applications

Abstract— Reduced‐voltage differential signaling (RVDS) is a novel interface for TFT‐LCD panels with a chip‐on‐glass (COG) structure, which has a point‐to‐point topology and a voltage mode differential signaling scheme. The voltage‐driving interface scheme has advantages in high‐speed operation owing to its relatively small time constant for the resistive channel condition. And reduced‐voltage signaling can reduce the power consumption of a transmitter. The display source driver IC with an RVDS interface, which is fabricated by using a 0.25‐μm CMOS process with a 2.5‐V logic supply voltage, offers a high data rate up to 500 Mbps, low‐current consumption of 2.2 mA, and good EMI characteristics. Also, an RVDS interface has programmable options that control the bandwidth, system power, and EMI performance. Therefore, the RVDS interface is a competitive solution for low‐power, low‐cost, and slim notebook applications.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

A high image quality organic light‐emitting diode display with motion blur reduction for ultrahigh resolution and premium TVs

In this paper, we present a high image quality organic light‐emitting diode (OLED) display with motion blur reduction technology. Our latest work includes driving method that reduces motion blur using an adaptive black data insertion, brightness compensation technology, the simple structure pixel with low capacitance coupling for horizontal noise, and the multifunction integrated gate driver. The moving picture response time (MPRT) value of the OLED display panel with a fast response time was significantly affected by the frame frequency and the compensation driving method. The MPRT value of the large‐size OLED display panels was significantly decreased by using the integrated gate driver circuit with an MPRT reduction method. The decrease in the MPRT value originated from the turning of the emitting pixels off in advance resulting from providing black data. The integrated gate drivers were designed to achieve the normal display, the black data insertion, and the compensation mode. The MPRT value of the 65‐in. ultrahigh‐definition (UHD) OLED panels was decreased to 3.4 ms by using an integrated gate driver circuit. The motion blur of large‐size OLED display panels was significantly reduced due to a decrease in the MPRT value.     

Compact and power‐saving polysilicon data driver with common‐decoder DA converter (CD‐DAC)

Abstract— A common‐decoder architecture for a data‐driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low‐power consumption. In application to an integrated polysilicon data driver for small‐sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word‐to‐word transitions from six to two. By using a conventional 4‐μm design rule, we fabricated an active‐matrix OLED (AMOLED) panel with an integrated six‐bit data‐driver circuit with 384 outputs. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic‐data transfer and 1.2 mW for reference‐voltage source. Furthermore, we also fabricated an active‐matrix LCD (AMLCD) panel including driver circuits of the same type as the integrated elements. Six‐bit full‐color images were successfully displayed on both panels.     

Advanced impulsive‐driving technique for Super‐PVA panel

Abstract— Super‐PVA (S‐PVA) technology developed by Samsung has demonstrated excellent viewing‐angle performance. However, S‐PVA panels can place extra demands on charging time due to the time‐multiplexed driving scheme required to separately address two subpixels. Specifically, a 2G‐1D pixel structure theoretically requires subpixel charging in one‐half of the time available for a conventional panel. In this paper, a new LCD driving scheme, super impulsive technology (SIT), is proposed to improve motion‐blur reduction by driving an S‐PVA LCD panel at 120 Hz. The proposed scheme allows a 120‐Hz 2G‐1D panel to be driven with an adequate charging‐time margin while providing an impulsive driving effect for motion‐blur reduction. Considering that the cost of a 2G‐1D S‐PVA panel is comparable to that of a conventional 60‐Hz panel, this method achieves good performance at a reasonable price. The detailed algorithm and implementation method are explored and the performance improvements are verified.     

IGZO‐TFT technology for large‐screen 8K display

We succeeded in G8 factory for mass production of Indium–Gallium–Zink–Oxide thin‐film transistor (IGZO‐TFT) for the first time in the world. The initial TFT process was an etching stop‐type TFT, but now, we are mass producing channel etching‐type TFTs. And, its application range is smartphones, tablets, PCs, monitors, TV, and so on. In particular, because of recent demands for high‐resolution and narrow frame, our IGZO display has been advanced in technology development with gate driver in panel. In this paper, we report development combining low resistance technology and the latest IGZO‐TFT (IGZO5) for large‐screen 8K display.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

120 Hz low cross-talk stereoscopic display with intelligent LED backlight enabled by multi-dimensional controlling IC

This paper proposes to employ multi-dimensional controller for driving LED backlight scanning in a 120 Hz LCD for overcoming the hold-type characteristic of an LCD in time-multiplexed stereoscopic displays. A synchronization signal circuit is developed to connect the time scheme of the vertical synchronization for reducing scanning time. The general strategy is to integrate 3D controller and all relatively small-signal electronic functions into one ASIC to minimize the total number of the components. The display panel, LED backlight scanning, and shutter glass signals could be adjusted by vertical synchronization and modulation to obtain stereoscopic images. Each row of LED in a backlight module is controlled by multi-dimensional data registration and synchronization control circuits for LED backlight scanning to flash in bright or dark. LED backlight scanning stereoscopic display incorporated with shutter glasses is provided to realize stereoscopic images even viewed in a liquid crystal display. The eye shutter signal is alternately switched from the left eye to the right eye with 120 Hz of LCD Vertical synchronization (V-sync). This kind of low cross-talk shutter glasses stereoscopic display with an intelligent multiplexing control of LED backlight scanning has low cross-talk below 1% through a liquid crystal shutter glasses.     

Fully‐integrated active matrix programmable UV and blue micro‐LED display system‐on‐panel (SoP)

High pixel per inch and high‐resolution micro‐LED displays are attracting more and more attentions. The increasing pixel number requires a large amount of bonding pads and brings huge difficulties to micro‐LED system design and lowers power efficiency as well. It is urgent to integrate row and column driving circuits onto the micro‐LED panel. Here, we report a fully integrated active matrix programmable micro‐LED system on panel (SoP) with ultraviolet and blue emission wavelengths. The micro‐LED SoP has a resolution of 60 × 60 and pixel pitch of 70 μm. The micro‐LED SoP was achieved by integrating micro‐LED arrays with silicon‐based p‐channel metal‐oxide semiconductor driving panel using fine‐toned flip‐chip bonding technology. With fully integrated scan and data circuits, the number of bonding pads was greatly reduced from 136 to 28, and large amount of metal interconnection lines were saved. The micro‐LED SoP panel was mounted on a periphery driving board, and representative characters were displayed successfully.