SiH_4-NH_3-N_2体系LPCVD氮化硅薄膜的生长动力学

以硅烷和氨气分别作为低压化学气相沉积(LPCVD)氮化硅(SiNx)薄膜的硅源和氮源,以高纯氮气为载气,在热壁型管式反应炉中,借助椭圆偏振仪和原子力显微镜,系统考察了工作压力、反应温度、气体原料组成等因素对SiNx薄膜沉积速率和表面形貌的影响。结果表明:SiNx薄膜的生长速率随着工作压力的增大单调增加,随着原料气中氨气与硅烷的流量之比的增大单调减小。随着反应温度的升高,沉积速率逐渐增加,在840℃附近达到最大,随后迅速降低。在适当的工艺条件下,制备的SiNx薄膜均匀、平整。较低的薄膜沉积速率有助于提高薄膜的均匀性,降低薄膜的表面粗糙度。     

流量及温度对低频PECVD氮化硅薄膜性能的影响

研究了低频等离子增强化学气相沉积(LF-PECVD)工艺中气体流量比和衬底温度对氮化硅薄膜折射率、密度及应力的影响规律,同时测试了薄膜的红外光谱以分析不同条件对薄膜成分的影响.结果表明,低频氮化硅薄膜折射率主要受薄膜内硅氮元素比的影响,其次是薄膜密度的影响.前者主要由硅烷/氨气反应气体流量比决定,而后者主要由衬底温度决定;低频氮化硅薄膜应力大致与密度成正比关系.此外,PECVD工艺所制备氮化硅薄膜都含有相当数量的氢元素,而衬底温度是薄膜内氢含量的决定因素.     

LPCVD氮化硅薄膜工艺研究

氮化硅薄膜在半导体器件制造、薄膜加工、MEMS中有着广泛的应用。利用低压化学气相淀积（LPCVD）技术,在800℃温度下,不同的工艺气体流量比生成的氮化硅薄膜,其薄膜成份中的硅氮比会有不同,造成薄膜特性也不同。通过测试氮化硅薄膜在缓冲腐蚀液（BOE）中的腐蚀速率,来推定氮化硅所含硅氮成分,寻找出适合生产的最佳工艺条件。     

适用于沉积工艺的真空技术

半导体生产中的薄膜沉积工艺通常对真空泵的要求很严格。在该工艺中高故障率和停机现象较为普遍。iH真空泵是特别为应付恶劣的薄膜工艺环境所设计。阐述了iH系列干泵在LPCVD氮化硅工艺应用中的成功表现。     

用于纳米级芯片制造的基于单晶圆LPCVD工艺

低压化学气相沉积（LPCVD）是化学气相沉积（CVD）的一个分支,同时也是半导体集成电路制造工艺中必不可少的重要工序之一。它主要用于多晶硅及其原位掺杂、氮化硅、氧化硅以及钨化硅等薄膜的生长。其基本原理是将一种或数种物质的气体,在低气压条件下,以热能的方式激活,发生热分解或化学反应,在衬底（如硅晶圆）表面沉积所需的固体薄膜。     

正交试验法优选LPCVD最佳工艺

本文采用正交试验法,经过次数不多的试验,在一台未能正常使用的LPCVD设备上,优选出淀积氮化硅薄膜的最佳工艺.上述工艺找到了淀积氮化硅的一些规律,氮化硅薄膜在抗氧化能力、腐蚀速率、折射率.薄膜生长速率等方面都获好的水平.本方法也可用于半导体工艺改革和新产品的研制.     

SiH_2Cl_2-NH_3-N_2体系LPCVD氮化硅薄膜生长工艺

以自行研制的LPCVD设备所进行的工艺试验为基础,简要介绍了Si3N4薄膜的制备方法和LPCVD法制备的Si3N4薄膜的特性以及低压化学气相淀积(LPCVD)氮化硅的工艺。通过调节淀积温度、工艺气体流量、工艺压力及片距等工艺参数,最终使批量生产的氮化硅薄膜在均匀性、应力、耐腐蚀等方面均达到了使用要求。     

离子束增强沉积氮化硅薄膜生长及其性能研究

用离子束增强沉积技术合成了氮化硅薄膜并研究了薄膜的组分、性能和结构.结果表明,离子束增强沉积生长的氮化硅薄膜的组分比,可借助于调节氮离子和硅原子到达率之比加以控制.在合适条件下生长的氮化硅薄膜,其红外吸收特征峰在波数为840cm~(-1)附近,光折射率在2.2到2.6之间,其组分为Si_3N_4用RBS、AES、TEM、SEM、ED及扩展电阻,测量和观察生成的氮化硅薄膜的组分深度分布及结构.发现,离子束增强沉积制备的氮化硅薄膜,存在着表面富硅层、氮化硅沉积层及混合过渡层这样的多层结构.薄膜呈球状或方块状堆积.基本上是无定形相,但局部可观察到单晶相的存在.离子束增强沉积制备的氮化硅薄膜中的含氧量比不用离子束辅助沉积的显著减少.     

用SiH_4-NH_3体系减压化学汽相淀积氮化硅薄膜的工艺研究

近些年来,使用扩散炉由减压方式产生的化学汽相淀积技术(简称LPCVD技术),在一些技术发达的国家中已有很大的突破和进展,国内对这项技术也引起了极大的重视,并且取得了较快的进展。LPCVD技术所以能被迅速的接受,是由于它采用密集垂直装片方式,生产量大,效率高。同时,它在一个固定的电阻炉内硅片直接受热,在低压下可以导致淀积非常均匀的薄膜厚度和组份。 采用LPCVD技术淀积多晶硅、氮化硅、二氧化硅和磷硅玻璃等薄膜,近些年国外不断有所报导。表1列出了各种淀积膜的现状。 近两年来用LPCVD技术淀积多晶硅、氮化硅薄膜国内也有些报导。特别是LPCVD多晶硅报导的较多,进展较显著,问题点也不多。而LPCVD氮化硅薄膜与多晶硅比较,生长     

应用高频激励源制备低应力氮化硅薄膜研究

研究了在等离子体增强化学气相沉积(PECVD)法制备氮化硅薄膜时,射频功率和腔室压力对氮化硅薄膜应力的影响以及应力与沉积速率的关系。通常认为高频下制备得到的氮化硅膜呈现张应力,但是通过实验,表明即使应用高频(13.56MH z)作为激励源同样可以沉积出呈现压应力的氮化硅薄膜。并使用角度可变光谱型椭偏仪观察了薄膜的厚度和低应力氮化硅膜的m app ing图,利用傅立叶变换红外光谱仪(FT IR)对不同应力状态下的氮化硅膜的化学键结构进行了分析。     

LPCVD silicon nitride uniformity improvement using adaptive real-time temperature control

An effective approach to improve silicon nitride thickness uniformity has been demonstrated on a batch LPCVD furnace platform. Implementation of adaptive real-time temperature control provides accurate, real-time estimation of substrate temperature profiles that enables model-based optimization of process temperature. Optimization of a 200-nm silicon nitride deposition yielded long-term, overall nitride thickness uniformity of 0.79% 1/spl sigma/ over a seven-week period, compared to 1.24% for an equivalent PID-tuned process. Three sequential silicon nitride deposition iterations were implemented in the process recipe to enable increased temperature ramp rates for more efficient optimization of within-wafer uniformity. The optimized process requalified quickly after major and minor equipment maintenance, and is suitable for use in a manufacturing environment. The ART-optimized temperature ramp intervals used in this study are comparable to temperature deltas often used to offset dichlorosilane depletion effects encountered in some large-batch vertical furnace depositions. SIMS depth profiling of ART-optimized silicon nitride does reveal small oxygen and chlorine peaks, indicating slight interface formation between deposition steps.     

炉管制程工艺中的片数效应及其优化方案

随着半导体技术的发展,越来越多的立式炉管在200mm及300mm集成电路晶圆制造中被应用到。同时炉管制程中的片数效应随着集成电路芯片的集成度越来越高而被凸显出来。文章将以LPCVD氮化硅在0.16μm、64M堆叠式内存制造过程中的片数效应为例,阐述炉管制程工艺中的片数效应以及通过调整制程参数（温度、沉积时间）的方式予以解决的实例。文中通过调整炉管上中下的温度来补偿气体的分布不均匀,调整沉积时间来补偿不同片数的沉积速率的差异,两者结合并辅以基于片数的分片程式来解氮化硅电介质沉积的片数效应。同时以此为基础总结出炉管片数效应的解决方案。     

LPCVD制备二氧化硅薄膜工艺研究

采用TEOS源LPCVD法制备了SiO2薄膜,采用膜厚仪对薄膜的厚度进行测试.通过不同条件下SiO2薄膜的厚度变化,讨论了TEOS源温度、反应压力及反应温度等工艺条件对淀积速率和均匀性的影响.结果表明,在40℃,50 Pa左右,淀积速率随TEOS源温度、反应压力基本呈线性增大.通过多次试验改进,提出了SiO2膜淀积的典...     

A methodology for optimizing a constant temperature polysilicondeposition process

A three-step approach to characterizing a low pressure chemical vapor deposition (LPCVD) constant temperature polysilicon process is discussed. This approach optimizes an LPCVD polysilicon process for both film uniformity and particles. The first step is to design and construct a constant deposition temperature polysilicon furnace to provide the best system performance possible in terms of particle generation and improved film uniformity. The second step is to characterize a process in this newly constructed furnace for both film uniformity and particles by using an experimental design that incorporated an L₁₈ orthogonal array. The hydrogen chloride preclean flow prior to deposition plays a key role in both defect generation and film uniformity. Both capacitance-voltage techniques and secondary ion mass spectrometry are used to understand this role. The third step is to verify the recommended setting from the experimental design by processing confirmation runs. Results from the confirmation runs in the optimally constructed polysilicon furnace show that particles can be reduced by up to 66% and film uniformity can be improved by 29% over the current production process     

In situ measurement of wafer temperatures in a low pressurechemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer     

Effects of deposition temperature on the oxidation resistance andelectrical characteristics of silicon nitride

A study was made of the effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride. It was found that silicon nitride below a certain limit thickness has no oxidation resistance. This threshold falls as the deposition temperature is lowered. 3-nm-thick silicon nitride deposited at 600°C has sufficient oxidation resistance For wet oxidation at 850°C, while 5 nm film deposited at 750°C has no oxidation resistance. The electrical characteristics also improve as the deposition temperature is lowered. 6-nm-thick silicon nitride deposited at 600°C shows a TDDB lifetime that is about two orders longer than that of 6-nm-thick silicon nitride deposited at 700°C. It was also found that the silicon nitride transition layer which is deposited at the initial stage of deposition influences the oxidation resistance and electrical characteristics of thin silicon nitride. It was concluded that lowering the deposition temperature reduces the influence of the transition layer and improves the oxidation resistance and electrical characteristics of thin silicon nitride     

p-Si TFT栅绝缘层用SiN薄膜的研究

以NH3和SiH4为反应源气体,采用射频等离子体增强化学气相沉积(RF-PECVD)法在多晶硅(p-Si)衬底上沉积了一系列SiN薄膜,并利用椭圆偏振测厚仪、超高电阻-微电流计、C-V测试仪对所沉积的薄膜作了相关性能测试.系统分析了沉积温度和射频功率对SiN薄膜的相对介电常数、电学性能及界面特性的影响.分析表明,沉积温度和射频功率主要是通过影响SiN薄膜中的Si/N比影响薄膜的性能,在制备高质量的p-Si TFT栅绝缘层用SiN薄膜方面具有重要的参考价值.     

淀积参数对PECVD氮化硅薄膜力学特性的影响

等离子增强化学气相淀积(PECVD)法制备的氮化硅薄膜具有沉积温度低、生长速率高和残余应力可调节等特点,研究其力学特性对研制MEMS器件和系统具有重要意义。采用HQ-2型PECVD淀积台,在沉积温度为350℃,NH3流量为30cm3/min的条件下,通过改变氩气稀释至5%的SiH4流量和射频功率大小,制备了具有压应力、微应力和张应力的多种氮化硅薄膜样品。采用纳米压痕仪Nanoidenter-G200对淀积薄膜的杨氏模量和硬度进行测试,结果表明,在较小的SiH4流量和较高的射频功率条件下,淀积的氮化硅薄膜具有更高的杨氏模量和硬度。     

Silicon nitride thin-film deposition by LPCVD with in situ HF vaporcleaning and its application to stacked DRAM capacitor fabrication

Silicon nitride film deposited by LPCVD with newly developed in situ HF vapor cleaning has been studied and applied to fabricate dielectric films for stacked DRAM capacitors. Using this method, an oxide-free surface of underlaid poly-Si can be obtained. Silicon nitride film deposited on this surface has been verified by FTIR measurement to have the stoichiometrically proper composition of Si₃N₄ . However, the film was found to be selectively deposited on poly-Si electrodes. This selective deposition degrades the reliability of the stacked capacitor, because the silicon nitride can not completely cover the periphery of poly-Si electrodes on SiO₂. We propose a simple process that avoids the problem making it possible to apply silicon nitride film to stacked-capacitor fabrication. Stacked capacitors fabricated by this process exhibit very low leakage current and high electrical reliability even for ultra-thin silicon nitride films less than 5 nm thick