IEEE 802.16a RS-CC编解码及DSPs实现

依托TMS320C6201 EVM设计具有AD和DA的扩展子板，同时给出RS-CC编解码系统的DSP设计思路和实现方案，最后完成该编解码系统，译码速率可达147．2kbps。     

基于VCP的卷积码译码算法研究

目前,Viterbi译码算法主要是在DSP或FPGA中用软件算法来实现,算法复杂度高,译码效率低。针对此问题,介绍TI公司的TMS320C6416 DSP芯片上的维特比协处理(VCP)的结构与原理。对无线通信系统广泛采用的卷积码译码进行研究,用VCP单独进行译码,与DSP的数据交换可以采用增强型DMA(EDMA)来完成,从而用硬件方法实现并行处理,提高译码效率。仿真结果表明使用VCP译码可在降低运算量和占用资源的基础上取得良好系统性能。     

基于DSP的Viterbi译码器

研究了数字信号处理(DSP)在移动通信中的应用,主要是Viterbi信道译码算法(VA)的DSP实现,在研究Viterbi译码算法原理的理论基础上,重点研究了DSP实现方法.     

OFDM系统中基于定点DSP的LDPC译码器仿真与实现

对译码算法进行了简化，实现了基于TMS320C6416定点DSP的LDPC译码器，结果表明，使用简化算法能有效降低译码复杂度，降低成本。提高译码速度和数据吞吐率。     

WiMAX系统中RS-CC级联码的算法研究

保证在高速数据传输的情况下提供可靠的服务质量,信道编码是解决此问题的有效途径。文章重点研究了WiMAX系统中RS-CC级联码的编译码技术,尤其是RS编译码和卷积码的Viterbi算法。     

Turbo译码器的log_MAP算法及其实现

首先讲述了Turbo编译码的原理,然后主要对Turbo译码的最大后验概率(MAP)算法演化而来的可实现的log_MAP译码算法进行了研究。最后讨论了log_MAP算法在数字信号处理器(DSP)中的实现。     

一种改进的Max-Log-Map译码算法的DSP实现

针对传统的Max-Log-Map译码算法时效性差、存储空间开销大的特点,本文对传统的Max-Log-Map译码算法进行了改进。改进的算法对前、后向度量使用了蝶形结构图,便于DSP实现;将原始帧均分为多个子块,设计子块间的并行运算以减小系统延迟;子块内采取进一步地优化措施,以减小数据存储量并提高译码速率。在DSP C6416平台上的仿真结果表明了算法的可实现性与可靠性。     

EKA扩展译码算法优化及其DSP实现研究

软件无线电接收机对实时性的要求很高,必须选择执行速度较快而又节省存储空间的译码方式。介绍了格雷码的扩展译码算法(EKA)[1],并与其他算法进行了比较。提出了扩展格雷码的译码方案,在基于DSP的软件无线电接收机中实现了EKA算法并进行了优化。通过实验结果和实际应用可知,EKA算法的执行效率优于文中介绍的其他算法,并可以实现扩展格雷码的实时译码。     

Viterbi译码算法在55系列DSP上的C语言实现

为了在DSP中实现Viterbi译码,用C语言编程实现了一种全并行连续译码的Viterbi译码算法。其各功能模块用函数设计,纠错性能的测试和验证采用文件读写的方法,便于处理大容量的编译码数据,且能容易地修改错误的形式。仿真测试结果表明,该Viterbi译码算法的纠错性能完全达到甚至优于Viterbi理论算法纠错性能的极限,采用C语言设计,程序可读性好,且便于在不同系列DSP平台之间移植。     

基于TMS320C54xx的RS码软判决译码的实现

介绍了一种基于改进型Chase算法的RS(Reed-Solomon)码软判决译码方法,阐述了该方法在信道编码应用中的核心思想,比较了各种Chase算法的优劣,并对RS(14,10)码的自适应软判决译码算法在DSP中的实现方法进行了研究,提出了用翻转表法实现试探序列的快速产生方法.实验证明该译码算法效率高,纠错能力强,适合实时性要求高的数据通信场合.     

一种基于模运算和扩展欧几里得定理的喷泉码

针对中国剩余定理在模运算喷泉码译码过程中的固有不足,本文提出一种全新的基于扩展欧几里德定理的译码算法.该算法采用合并线性同余方程组,避免分解因子非互质情况下求解乘率因子失败的问题.模运算喷泉码将信息数据编码为自然数分解因子和相对应的模余数的数据包,接收方只要获取一定数目的编码数据包就能成功解码.基于扩展欧几里得定理的译码算法扩展了模运算喷泉码的分解因子范围,提高了编译码效率.本文通过理论分析和数值仿真证实了这种编译码算法的可行性.     

喷泉码编译码原理研究和分析

喷泉码是一种新颖的基于图的纠删码技术,在工程应用上有广阔的前景。本文针对几种典型分布数字喷泉码的编码方式进行综合比较和规律总结,同时对喷泉码的两类译码方式和适用范围进行了分析与探讨,通过仿真数据和图形比较了不同分布编码方式的性能差异和不同译码方式的优缺点所在。     

DRA算法及其实时解码器设计

DRA是一种新的音频编解码标准,其在每声道64 Kbit/s时重建的音质达到ITU-R规定的"人耳不可识别损伤"的主观音质评定.研究了DRA的编码与解码原理,在对解码算法进行了优化的基础上.设计并实现了基于PXA270平台的DRA实时解码器.主观听音测试结果表明.该解码器音质良好.满足实时解码应用的要求.     

Turbo trellis coded modulation for transform domain distributed video coding

A transform domain distributed video coding (DVC) codec is proposed using turbo trellis coded modulation (TTCM). TTCM symbols are generated at the DVC decoder using the side information and the parity bits received from the DVC encoder. These generated symbols are used at the TTCM-based DVC decoder to decode the bit stream. Simulation results show that a significant rate-distortion performance gain can be achieved using the proposed codec compared to the best state-of-the-art transform domain DVC codecs discussed in the literature.     

Real-Time Software Video Codec with a Fast Adaptive Motion Vector Search

A PC-based real-time software MPEG-4 video codec with a fast adaptive motion vector search is presented. In a fast adaptive motion estimation (ME) technique, the search order is dynamically changed in according with the motion of objects. This technique suppresses load fluctuation in the ME and contributes to the stable real-time work of the software codec. MMX instructions are used to increase the codec speed. On a portable PC, the software video codec supports satisfactory mobile visual communication at 64 kbps and 128 kbps, for example, at QCIF 15 fps. The codec on a 450 MHz PentiumII processor can encode and decode 30 CIF frames in real-time.     

Design of Reed-Solomon (16,12) codec for North American AdvancedTrain Control System

The design of the codec for the ATCS radio data link is considered. The code is defined. The encoding algorithm, the decoding algorithm, and Galois field arithmetic are discussed. Implementation of the Reed-Solomon codec as a stand-alone system in order to provide a possibility of real-time bit-rate measurement is discussed. The implementation of this codec using three different 8-b and 16-b microprocessors/microcomputers is described. Their complexity and throughput are discussed     

低比特率音频编解码在嵌入式平台中的移植与优化

本文描述了AMR—WB＋音频编解码的结构框架,复杂性,移植和优化。AMR—WB＋编解码在低码率范围内表现出相当优秀的品质,并且在各种音频类型上都有一致的高性能。因此被3GPP和DVB选定为移动网络中低码率音频指定编解码算法。     

Arithmetic coding-based continuous error detection for efficientARQ-based image transmission

Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new “continuous” error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection, first introduced by Bell, Witten, and Cleary (1990), is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error     

基于FPGA的曼彻斯特编解码器设计

自上世纪80年代以来,MIL-STD-1553B总线标准已广泛应用于海陆空三军,但是其核心编解码芯片多为国外生产,为实现自主研发,设计出基于FPGA的曼彻斯特编解码器是影响整个总线系统通信质量的关键。本设计采用硬件描述语言(Verilog)设计电路,ISE完成综合和布局布线的工作,并用modelSim进行仿真验证。在深入分析曼彻斯特码型特点的基础上,对编解码器的工作过程和逻辑结构进行详细介绍。     

Error-Resilient Performance of Dirac Video Codec Over Packet-Erasure Channel

Video transmission over the wireless or wired network requires error-resilient mechanism since compressed video bitstreams are sensitive to transmission errors because of the use of predictive coding and variable length coding. This paper investigates the performance of a simple and low complexity error-resilient coding scheme which combines source and channel coding to protect compressed bitstream of wavelet-based Dirac video codec in the packet-erasure channel. By partitioning the wavelet transform coefficients of the motion-compensated residual frame into groups and independently processing each group using arithmetic and forward error correction (FEC) coding, Dirac could achieves the robustness to transmission errors by giving the video quality which is gracefully decreasing over a range of packet loss rates up to 30% when compared with conventional FEC only methods. Simulation results also show that the proposed scheme using multiple partitions can achieve up to 10 dB PSNR gain over its existing un-partitioned format. This paper also investigates the error-resilient performance of the proposed scheme in comparison with H.264 over packet-erasure channel.