Influence of source-drain series resistance on MOSFET field-effect mobility

A simple but general model for explaining the series resistance dependence of transconductance and field-effect mobility is developed in the letter. This model, which enables a quantitative analysis of series resistance effects on the maximum mobility and the corresponding gate voltage, has been successfully tested on short-channel MOSFETs with various channel lengths and external series resistances.     

A review of DC extraction methods for MOSFET series resistance and mobility degradation model parameters

The performance of modern MOSFETs is limited by the presence of parasitic series resistances and mobility degradation. This article reviews and assesses 18 of the extraction methods currently used to determine the values of parasitic series resistances and mobility degradation from the measured drain current. The methods are separated in 3 groups: seven different methods that use the transfer characteristics of several devices having different mask channel lengths; five methods based on a single device with different drain and gate bias; six methods which account for the asymmetry between drain and source resistance.     

Extraction of bias-dependent parasitic source/drain resistance in MOSFETs with an advanced mobility model

We present a new method to extract gate-bias-dependent source/drain resistance in MOSFETs. The extraction starts from a simple mobility model, but a more sophisticated mobility model is incorporated afterward. The method provides a convenient way to extract the source/drain resistance as well as parameters in a sophisticated mobility model. The extracted parameters in the mobility model vary with channel length. To satisfy some device modeling work where parameters independent of channel length are desirable, we also develop another technique so that a single set of parameters is obtained and is applicable to all channel lengths. The extraction techniques are useful for submicron MOSFETs without going through complicated procedure.     

Determination of gate-bias dependent source/drain series resistance and effective channel length for advanced MOS devices

In this paper, an improved method for determining the gate-bias dependent source and drain series resistances R_D and effective channel length L_eff = L_M − ΔL (L_M is the mask channel length and ΔL is the channel length reduction) of advanced MOS devices is developed for the purpose of providing a better accuracy for the modeling of the current–voltage characteristics of LDD MOSFETs operating from 25 to 120 °C. Our results show that both ΔL and R_SD decrease with increasing gate-bias, but increase with increasing temperature. In addition, the gate-bias dependence of ΔL and R_SD becomes weaker as the temperature rises. Experimental data obtained from devices fabricated using the 0.14 and 0.09 μm DRAM technologies are included in support of the theoretical work developed.     

Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices

In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source–drain resistance with stress time. It is suggested that the origin of the time-dependent increasing source–drain resistance is the injection of charge, either in the form of fixed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modified to account for these new observations.     

Influence of series resistance in oxide parameter extraction data from accelerated tests

Accelerated reliability tests on thin oxide capacitors can be affected by series resistance effects at high stress conditions. The purpose of this work is to point out such problems both with measurements and simulations. It is shown that breakdown electric field is overestimated. Due to the resulting nonuniform stress, charge to breakdown density is underestimated if the test structure layout is not accurately designed. In any case the series resistance effects can have an undesirable impact on the reliability evaluation of thin dielectrics.     

On the extraction of the source and drain series resistances of MOSFETs

This article reviews and scrutinizes various proposed methods to extract the individual values of drain and source resistances (R_D and R_S) of MOSFETs, which are important device parameters for modeling and circuit simulation. In general, these methods contain three basic steps: (1) the extraction of the total drain and source resistance (R_D+R_S); (2) the extraction of the difference between the drain and the source resistances (R_D−R_S); and (3) the calculation of R_D and R_S from the knowledge of (R_D+R_S) and (R_D−R_S). These methods are tested and compared in the environments of circuit simulator, device simulation and measurements.     

An analytical drain current model of short-channel MOSFETs including source/drain resistance effect

In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance (R _S/R _D). Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the R _S and R _D can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the R _S/R _D increases with decreasing channel length and oxide thickness.     

Precise quantitative evaluation of the hot-carrier induced drain series resistance degradation in LATID-n-MOSFETs

A method is presented which allows to distinguish the drain series resistance increase from other mechanisms contributing to the drain current degradation of hot-carrier stressed n-MOSFETs. Devices with different channel lengths but equal damages are used. The different degradation mechanisms are characterized quantitatively and a model for the drain current degradation is presented. For short stress times, the drain current degradation is dominated by series resistance degradation. For long stress times, however, the contribution of the mechanisms attributed to an “equivalent channel length increase” prevails.     

A 2DEG charge density based drain current model for various Al and In molefraction mobility dependent nano-scale AlInGaN/AlN/GaN HEMT devices

We present a two-dimensional electron gas（2DEG） charge-control mobility variation based drain current model for sheet carrier density in the channel.The model was developed for the AlInGaN/AlN/GaN highelectron -mobility transistor.The sheet carrier density model used here accounts for the independence between the Fermi levels E_f and n_s along with mobility for various Al and In molefractions.This physics based ns model fully depends upon the variation of E_f,u0,the first subband E₀,the second subband E\,and n_s.We present a physics based analytical drain current model using n_s with the minimum set of parameters.The analytical results obtained are compared with the experimental results for four samples with various molefraction and barrier thickness.A good agreement between the results is obtained,thus validating the model.     

Evaluation of voltage dependent series resistance of epitaxial varactor diodes at microwave frequencies

The series resistance of a high-quality varactor diode is primarily determined by the resistance of the semiconductor material close to the junction. With increasing reverse bias, the width of the space-charge region becomes greater, and the series resistance decreases. Theoretical models of graded and step junctions have been assumed, and calculations have been made of the series resistance as a function of bias. Epitaxial silicon diodes have been measured for series resistance as a function of bias by using the transmission loss method at 6 to 12 Gc/s, with the diode mounted across a reduced-height waveguide. The variation of series resistance with bias agrees well with the theoretical calculations. By measuring of the 3-dB bandwidth of the series resonance of the diode mounted in the reduced-height waveguide, the junction capacitance and the effective series inductance of the package also can be determined. Because the width of the space-charge region must vary with applied voltage in order to obtain the varactor characteristic, the diode cannot have zero-series resistance at zero-volt bias. The minimum possible series resistance is a function of the breakdown voltage and increases with increasing breakdown voltage. Calculations of the maximum possible cutoff frequency as a function of the diode breakdown voltage are presented for both graded and step junction silicon varactors. A plot of series resistance vs. reverse bias can be used to determine the impurity concentration profile in the epitaxial film. The impurity concentration profile can also be determined by measuring the capacitance vs. reverse bias, a technique which has been in use for some time. However the former method appears to be more accurate in that it is independent of junction area.     

Influence of series resistance on guidelines for manufacture of concentrator p‐on‐n GaAs solar cells

This paper deals with the determination of the main factors influencing series resistance in p‐on‐n GaAs solar cells working at concentration levels of 1000 suns or higher. Prior to this analysis, a comparison between different front metal grid geometries is presented to show the strong influence that the front grid component of series resistance exerts on its global value. Once the inverted square grid geometry is selected, a detailed analysis of the different components of series resistance is carried out. For this purpose, a multidimensional optimisation of the whole GaAs solar cell (antireflecting coatings, series resistance and semiconductor structure) has been used for the first time. In order to orient the manufacture of very high concentrator GaAs solar cells, recommendations on the threshold values of solar cell size, specific p‐ and n‐contact resistances, thickness of the front metal grid and both doping level and thickness of the substrate are formulated. Several traditional ideas on the influence of these parameters are questioned. Copyright © 2000 John Wiley & Sons, Ltd.     

Analytic expression for the Fowler–Nordheim V–I characteristic including the series resistance effect

It is shown in this communication that the Fowler-Nordheim (FN) tunneling expression for the current-voltage (I-V) characteristic can be analytically inverted so that an exact expression for the voltage-current (V-I) characteristic can be obtained. The solution of the resulting implicit equation is found using the Lambert W function, i.e. the solution of the transcendental equation we^w = x. The reported expressions are supported by experimental I-V curves measured in thin (≈5 nm) SiO₂ films in MOS capacitors. The analysis includes the case of a tunneling oxide with a large series resistance. For practical purposes, a closed-form expression for W based on a Padé-type approximation is also provided.     

Extraction of gate dependent source/drain resistance and effective channel length in MOS devices at 77 K

A new extraction technique for obtaining the parasitic source/drain resistance and the effective channel length of an MOS device at 77 K is presented. Unlike previous methods, both parameters are assumed to vary with the gate voltage. This results in positive and physically meaningful results at any temperature. Simulation results show that, in non-LDD devices, the source/drain resistance decreases and the effective channel length increases with gate bias, indicating that the gate dependence of both parameters is inherent to MOS devices.<>     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

On the profile of frequency dependent series resistance and dielectric constant in MIS structure

In this study, the frequency dependent of the forward and reverse bias capacitance-voltage (C-V) and conductance-voltage (G/ω - V) measurements of Al/SiO₂/p-Si (MIS) structures are carried out in frequency range of 10 kHz-10 MHz. The frequency dependence of series resistance (R_s), density of surface states (N_ss), dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_dc) are studied for these structure at room temperature. Experimental results show that both electrical and dielectric parameters were strongly frequency and voltage dependent. The ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased. Also, both the effects of surface states N_ss and R_s on C-V and G/ω - V characteristics are investigated. It has been seen that the measured C and G decrease with increasing frequency due to a continuous distribution of N_ss in frequency range of 10 kHz-1 MHz. The effect of R_s on the C and G are found noticeable at high frequencies. Therefore, the high frequencies C and G values measured under both reverse and forward bias were corrected for the effect of series resistance R_s to obtain real MIS capacitance C_c and conductance G_c using the Nicollian and Goetzberger technique. The distribution profile of R_s-V gives a peak in the depletion region at low frequencies and disappears with increasing frequencies.     

Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance

The electron mobility behaviour in submicron MOSFETs is studied in the temperature range of 77–300 K. As the effective channel length is reduced, the effective mobility as well as the field-effect mobility are found to decrease and to become less temperature dependent. These experimental results are explained by the influence of series resistance and effective channel length, which are both temperature dependent. The possibility of accurate determination of series resistance and “pure” mobility is demonstrated. A new method is proposed to determine submicron MOSFET channel length at low temperatures.     

基于线性混合光谱方法的时间序列植被覆盖度提取

为了准确地从遥感数据中获取城市植被覆盖度(VFC)信息,以线性混合光谱模型(LSMM)为原理基础,参考各城市端元模型,利用MODIS时间序列提取武汉研究区2007至2014年间植被覆盖度,获得植被覆盖度年际变化情况。在对遥感影像进行端元提取及确定时,结合四种城市端元模型分别对研究区植被覆盖度进行估算,并对像元分解精度作对比分析。结果表明,MODIS时间序列使用混合光谱分析法能够科学客观地实现对研究区植被覆盖度的提取,可以有效地进行周期性监测和分析研究区植被覆盖变化。     

An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors