六角形超结VDMOS器件的终端结构设计

为六角形超结VDMOS器件提出了一种结终端结构,该终端结构采用与有源区相似的六角形晶格结构,但P柱和N柱的宽度均为有源区原胞晶格的一半.重点讨论了P柱的数量对表面电场的分布及击穿电压等的影响,模拟结果证实该终端结构的击穿电压大于600 V,击穿点发生在终端与有源区之间的过渡区.     

单区JTE加场板终端结构的优化设计

为了提高芯片面积利用率,采用单区结终端扩展(JTE)与复合场板技术设计了一款700 V VDMOS的终端结构。借助Sentaurus TCAD仿真软件,研究单区JTE注入剂量、JTE窗口长度和金属场板长度与击穿电压的关系,优化结构参数,改善表面和体内电场分布,提高器件的耐压。最终在120.4mm的有效终端长度上实现了838 V的击穿电压,表面最大电场为2.03×10~5 V/cm,小于工业界判断器件击穿的表面最大电场值(2.5×10~5 V/cm),受界面态电荷的影响小,具有较高的可靠性,且与高压深阱VDMOS工艺兼容,没有增加额外的掩膜和工艺步骤。     

超结MOSFET功率器件的终端技术分析

为了改善超结MOSFET功率器件的终端击穿特性,提出了一种平面结终端技术,应用柱坐标下的泊松方程证明了这种技术的可行性。提出了超结功率器件终端技术的工艺实现方法并分析了终端结构的电压特性,使用这种超结终端技术仿真得到了一个600V的Coolmos。利用2维仿真软件Medici讨论了终端p柱的数量和宽度因素对击穿电压和表面电场的影响。结果发现,采用变间距的超结结构本身就可以很好地实现超结MOSFET功率器件的终端。     

提高台面型大功率晶体管高温特性的尝试

一、引言 近年来,用平面台式工艺制作硅低频大功率管在我国发展很快,由于采用台面结构消除了平面结的弯曲部份,结变成平坦的平面,对同一电阻率,除了双面保护环新结构外,台面管的击穿电压是最高的。但是由于磨角腐蚀以形成台面而使PN结裸露在外,这就带来了台面容易沾污的问题,使PN结表面在器件工作温度下会产生较大的漏电流,使击穿电压下降因而器件容易穿通。所以对台面必须进行保护,从而使器件在较高的温度和一定的漏电流条件下具备较高的击穿电压,亦即使器件能有较好的使用性能和较高的可靠性。     

基于SM-JTE结构的4H-SiC器件

介绍了高压空间调制结终端扩展(SM-JTE)结构及其优势。结合实际的MOSFET工艺和已有的理论模型,定义了全新的4H-SiC器件TCAD仿真模型参数。首次提出了确定SM-JTE最优长度的方法。基于SM-JTE结构的4H-SiC器件具有优良的击穿特性。SM-JTE结构的长度为230 μm时,SM-JTE的击穿电压可以达到16 kV。针对界面电荷对击穿特性的影响进行了系统仿真研究。仿真结果表明,正界面电荷相比负界面电荷对击穿电压的影响更大,且界面态电荷会引起击穿电压明显下降。该SM-JTE结构可以采用更短的结终端,在同样尺寸的芯片上能制作更多的器件,从而提高生产效率,降低器件成本。     

台面刻蚀深度对埋栅SITH栅阴击穿的影响

针对台面刻蚀深度对埋栅型静电感应晶闸管(SITH)栅阴击穿特性的影响做了实验研究.实验结果表明,随着台面刻蚀深度的增大,器件栅阴击穿由原来的软击穿变为硬击穿,同时击穿电压升高,SITH设计了独立的台面槽,并研究了台面刻蚀深度与栅阴击穿电压和栅阴击穿特性间的关系,指出台面刻蚀深度的增加可以有效减弱表面电荷和表面缺陷对器件的影响,改善栅阴击穿曲线,提高栅阴击穿电压.同时,还简要描述了这种器件的制造工艺.     

一款700 V VDMOSFET结终端结构设计

为了提高功率器件结终端击穿电压,节约芯片面积,设计了一款700 V VDMOSFET结终端结构。在不增加额外工艺步骤和掩膜的前提下,该结构采用场限环-场板联合结终端技术,通过调整结终端场限环和场板的结构参数,在151μm的有效终端长度上达到了772 V的击穿电压,表面电场分布相对均匀且最大表面场强为2.27×105V/cm,小于工业界判断器件击穿场强标准(2.5×105 V/cm)。在保证相同的击穿电压下,比其他文献中同类结终端结构节约面积26%,实现了耐压和可靠性的要求,提高了结终端面积的利用效率。     

具有高压互连线的多区双RESURF LDMOS击穿特性

对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要.     

具有高压互连线的多区双RESURF LDMOS击穿特性

对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要.     

一种新型4H-SiC BJT结终端结构研究

设计了一种应用于4H-SiC BJT的新型结终端结构。该新型结终端结构通过对基区外围进行刻蚀形成单层刻蚀型外延终端,辅助耐压的p+环位于刻蚀型外延终端的表面,采用离子注入的方式,与基极接触的p+区同时形成。借助半导体数值分析软件SILVACO,对基区外围的刻蚀厚度和p+环的间距进行了优化。仿真分析结果表明,当刻蚀厚度为0.8μm,环间距分别为8,10和9μm时,能获得最高击穿电压。新结构与传统保护环(GR)和传统结终端外延(JTE)相比,BVCEO分别提高了34%和15%。利用该新型终端结构,得到共发射极电流增益β>47、共发射极击穿电压BVCEO为1 570V的4H-SiC BJT器件。     

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension (JTE) structures for 4H-SiC bipolar junction transistors (BJTs) with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device.     

Optimization and surface charge sensitivity of high-voltageblocking structures with shallow junctions

The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5×10¹¹ cm^-2 net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities     

Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zonejunction termination extension (JTE) have been employed to achieve a high breakdown voltage $(geq!hbox{10} hbox{kV})$ . The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of $hbox{1.1} times hbox{10}^{13} hbox{cm}^{-2}$ has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.      

Multiple-zone single-mask junction termination extension—A high-yield near-ideal breakdown voltage technology

The junction termination extension (JTE) technique of Temple is investigated in detail by computer simulation and experimentally. A multiple-zone JTE can be fabricated with a well-controlled single ion-implantation through a single mask with laterally variable transparencies. Analog I-V trace records of over 40 000 samples were obtained for analysis. By grouping 49 JTE designs onto region of the wafer, the effects of the JTE variations and the material variations are separated. The JTE performance agrees well with the computer results. The multiple-zone JTE of sufficient extension size achieves an essentially ideal breakdown voltage unaffected by even a factor of two in ion-implant dose variations. The JTE performs well on both n- and p-type wafers. A best design has been applied to several lots of power devices, and a yield of 99.5 percent having breakdown-voltage values within 10 percent of the ideal has been obtained. The single-mask technique assures the producibility of this 100-percent guard JTE technology, which consumes only 30 percent of the extension area needed by field rings that, at best, produced about 70 percent of the ideal breakdown voltage.     

高压VDMOSFET击穿电压优化设计

通过理论计算,优化了外延层厚度和掺杂浓度,对影响击穿电压的相关结构参数进行设计,探讨了VDMOSFET的终端结构。讨论了场限环和结终端扩展技术,提出了终端多区设计思路,提高了新型结构VDMOSFET的漏源击穿电压。设计了800V、6A功率VDMOSFET,同场限环技术相比,优化的结终端扩展技术,节省芯片面积10.6%,而不增加工艺流程,漏源击穿电压高达882V,提高了3%,由于芯片面积的缩小,平均芯片中测合格率提高5%,达到了预期目的,具有很好的经济价值。     

High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension

This paper presents the design and fabrication of an etched implant junction termination extension(JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.     

Optimization of junction termination extension for ultrahigh voltage 4H-SiC planar power devices

Numerical simulations on the optimization of junction termination extension (JTE) have been performed. Various termination techniques have been applied and simulated in this paper, such as single-zone JTE (S-JTE), multi-zone JTE (M-JTE), and space-modulated JTE (SM-JTE). A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE, and it is verified through simulation results. The simulation results show that the SM-JTE could provide a protection efficiency (defined in Section 2) of 95.2%, which is much higher than that of M-JTE (82.4%) and S-JTE (64.7%). Based on the fabricated MOSFETs, the interface charge density is extracted and the approximate range of charge density has been determined. The influences of different interface charge densities have been investigated for the three termination techniques respectively. According to the previous reports, the JTE is quite sensitive to the implanted dose, so the blocking capability of each termination structure with different implanted doses is also simulated. The results show that when interface charge is considered, the SM-JTE always shows an enormous advantage over the other two junction termination structures, however the interface charge densities varied. The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs, which would provide a very promising lower fabrication cost.     

Edge termination strategies for a 4 kV 4H–SiC thyristor

Thyristors able to block 4 kV have been fabricated and characterised. The experimental forward current is 1.3 A @ V_AK = 10 V for a 9 mA gate current during 550 ns. The device active area is 2.3 mm². The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO₂ passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5 kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4 kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6 kV. Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO₂ charge density provided by the different oxidation processes (at different foundries).In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO₂ layer in 10¹²–5 × 10¹² cm⁻² range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices.     

Optimization of interconnection-induced breakdown voltage injunction isolated IC's using biased polysilicon field plates

The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-μm wide wire     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.