Charge storage peculiarities in poly-Si–SiO2–Si memory devices with Si nanocrystals rich SiO2

The paper focuses on the study of charge trapping processes in non-volatile memory metal-oxide-silicon (MOS) structures with Si nanocrystal floating gate formed by Si ion implantation. Careful electrical studies of the MOS structures based on the analysis of the capacitance–voltage (C–V) characteristics during pulse charge injection in the oxide enabled the distinguishing of the electron emission from the nanoclusters and the charge trapping in structural defects of the dioxide matrix. The trapping model is discussed.     

New positive charge trapping dynamics in SiO2 gate oxide, based on bulk impact ionization processes under Fowler–Nordheim stress

A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO₂) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10^-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.     

Single band electronic conduction in hafnium oxide prepared by atomic layer deposition

Current–voltage and capacitance–voltage measurements on MOS structures with hafnium gate oxide (HfO₂) prepared by atomic layer deposition were conducted to determine the dominant current conduction in the Al/HfO₂/Si structure. In n-type substrate MOS structures, electron injection from Al into HfO₂ is observed when the Al electrode is negatively biased. Whereas in p-type MOS capacitors at negative biasing, no hole injection can be detected and the current in the insulator is again due to the electron injection from Al. These results unambiguously indicate that in both p- and n-type substrates and at both biasing polarities only electronic current conduction in the Si/HfO₂/Al is significant.     

Analytical investigation of surface potential and related properties of metal/insulator/III–V semiconductor capacitors

An analytical study of the effect of an applied gate bias on the potential and electron density in the semiconductor of metal/insulator/III–V semiconductor (III–V MIS) capacitors is carried out. For this, Poisson's equation is rewritten to a form amenable to analytical study. Si₃N₄ is used as an insulator layer for the MIS capacitors. In order to highlight the advantages of III–V MIS capacitors over metal-SiO₂---Si (MOS) capacitors, the ideal case free from interface traps is considered and theoretical results are obtained also for MOS capacitors. The calculated results strongly demonstrate the superiority of InGaAs MIS and GaAs MIS capacitors to Si MOS capacitors and pinpoint the situation in which the interface states are present.     

Reexamination of the role of nitrogen in oxynitrides-fixed chargereduction in the p+-polysilicon gate MOS

The problems associated with the use of p⁺-polysilicon gate MOS have been intensively investigated. Although the utilization of oxynitrides has been considered to be effective for the suppression of the threshold voltage (V_T) deviation in the p⁺-polysilicon gate MOSFETs, the investigation revealed that the p⁺-polysilicon gate MOS exhibits significantly different properties when oxynitrides contain no nitrogen at the oxynitride/substrate interface (MOS interface) than it does with usual oxynitrides which contain nitrogen at the MOS interface. This discrepancy arises because, contrary to what is usually considered to be the case, boron diffused into the substrate is not the origin of the negative fixed charge generated in the p⁺-polysilicon gate MOS structures, which is one of the most important factors influencing VT in those structures. We have found fluorine in the p⁺-polysilicon gate MOS structures even when the polysilicon is doped using boron ion implantation. This is a consequence of the use of BF₃ as a boron source. We propose a model in which fluorine is responsible for the negative fixed charge generation and nitrogen at the MOS interface prevents not only the boron penetration but also the negative fixed charge generation by suppressing the fluorine incorporation into the MOS interface     

Dependence of Fermi level positions at gate and substrate on thereliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υ_g^-). The oxide breakdown strength (Q_bd) is less for p⁺ poly-Si gate than for n⁺ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P⁺ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide     

Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET’s

The degradation of electrical performance induced by interface states is one main reason for failure occurs in deep-sub-micron MOS devices. Especially for grooved-gate MOS devices, there are a large amount of interface states and flaw formed during the etching of concave. Based on the hydrodynamics energy transport model, using MEDICI simulator, the degradation induced by donor interface states is analyzed for deep-sub-micron grooved-gate PMOSFET’s with different channel doping densities and compared with that of corresponding conventional planar PMOSFET’s. The results also compared with that of degradation induced by acceptor interface states. The simulation results indicate that the degradation induced by same interface state density in grooved-gate PMOSFET’s is larger than that in planar PMOSFET’s, and in both structure devices, the impact of electron donor interface states on device performance is far larger than that of hole donor interface state. This work gives an useful insight of mechanism of hot-carrier degradation for grooved gate MOS devices and lays a solid foundation for grooved gate devices used in deep-sub-micron region VLSI practically.     

Study of dc conduction mechanisms in dysprosium–manganese oxide insulator thin films grown on Si substrates

Samples of amorphous and crystalline (Dy–Mn) oxide thin films have been prepared on Si(p) substrates. The crystal structure of the oxide film annealed under different conditions was investigated by the X-ray diffraction method (XRD). The percentage weight composition of the compound-oxide films was determined by the X-ray fluorescence (XRF) spectroscopy method. It was observed that Dy oxide and Mn oxide prevent each other to crystallize alone or making a solid solution even at 600 °C, but a compound of DyMnO₃ was formed through the solid-state reaction at T > 800 °C. Samples in form of Al/oxide/Si MOS structures were characterised by measuring their capacitance as a function of gate voltage C(V_g) in order to determine the fixed and interface charge densities as well as the oxide voltage in terms of gate voltage. The total surface charge density was in the device-grade of 10¹⁰–10¹¹ cm⁻². The dc measurements at room temperature show that the main mechanism controlling the current flow is the Richardson–Schottky (RS) mechanism. The parameters of the RS model like the field lowering coefficients and the dynamic relative permittivity were determined. The leakage current density of the samples was studied as a function of temperature in a range of (293–380 K). It was observed that the temperature dependence of crystalline (Dy–Mn) oxide films has a property that higher temperature reduces the current, which may be important in the application in circuits that operate under extreme conditions. Thermal activation energies of electrical conduction were determined.     

The effects of gamma irradiation on low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The effects of gamma irradiation on as-deposited, oxygen-annealed, and dual-dielectric gate (undoped polysilicon/oxide) low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO₂) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO₂ MOS structures exhibit the largest shift in flatband voltage with gamma irradiation. This is most likely due to the large number of bulk oxide traps resulting from the nonstochiometric nature of as-deposited LPCVD SiO₂. Dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures exhibit the smallest shift in flatband voltage and increase in interface state density compared to as-deposited and oxygen-annealed LPCVD SiO₂ MOS structures. The interface state density of dual-dielectric MOS structures increases from 5 × 10¹⁰ eV cm⁻² to 2–3 × 10¹¹ eV cm⁻² after irradiation to a gamma total dose level of 1 Mrads(Si). This result suggests that the recombination of atomic hydrogen atoms with silicon dangling bonds, either along grain boundaries or in crystallites of the undoped polysilicon layer in dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures, probably reduces the number of atomic hydrogen atoms reaching the Si/SiO₂ interface to generate interface states.     

Experimental extraction of degradation parameters after constant voltage stress and substrate hot electron injection on ultrathin oxides

The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunnelling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by V_G and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunnelling.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.     

高压pLEDMOS器件在不同应力条件下导通电阻的衰退及改进方法

实验测试结果揭示高压pLEDMOS器件在不同的应力条件下,导通电阻的衰退结果不同,半导体器件专业软件MEDICI模拟结果表明Si/SiO2表面的陷阱产生以及热电子的注入和俘获导致了高压pLEDMOS器件在不同的应力条件下产生不同的导通电阻衰退.文中同时提出了一种改进方法:用场氧代替厚栅氧作为高压pLEDMoS器件的栅氧,MEDICI模拟结果显示该方法可以明显降低/减缓高压pLEDMOS导通电阻的衰退.