Hot electron induced degradation of undoped AlGaN/GaN HFETs

This work presents the effects of hot electron stress on the degradation of undoped Al_0.3GaN_0.7/GaN power HFET’s with SiN passivation. Typical degradation characteristics consist of a decrease in the drain current and maximum transconductance, an increase in the drain series resistance, gate leakage and a subthreshold current. Degradation mechanism has been investigated by means of gate lag measurements (pulsed I-V) and current-mode deep level transient spectroscopy (DLTS). Stressed devices suffered from aggravated drain current slump (DC to RF dispersion) which indicates possible changes in surface charge profiles occurred during hot electron stress test. The DLTS was used to identify the trap creation by hot electron stress. The DLTS spectra of stressed device revealed the evidence of trap creation due to hot electron stress.     

Slow transients observed in AlGaN/GaN HFETs: effects of SiN/sub x/ passivation and UV illumination

Very slow drain current and surface potential transients have been observed in AlGaN/GaN heterostructure field effect transistors that are subjected to high bias stress. Simultaneous measurements of drain current and surface potential indicate that large change in surface potential after stress is responsible for the reduction in drain current in these devices. Measurements of surface potential profile from the gate edge toward the drain as a function of time indicate that surface potential changes occur mostly near the gate. It is proposed that the surface potential changes are caused by electrons which tunnel from the gate under high bias stress and get trapped at the surface states near the gate. Passivation of the surface with SiN/sub x/ reduces the transient magnitudes to a large extent. This correlates with a large improvement in microwave power performance in these devices after passivation. UV illumination of these devices totally eliminates the drain current and surface potential transients.     

Improved reliability of AlGaN-GaN HEMTs using an NH/sub 3/ plasma treatment prior to SiN passivation

A passivation method has been developed which reduces the degradation of AlGaN-GaN high electron mobility transistor (HEMT) electrical properties caused by extended dc bias or microwave power operation. The key aspect of this passivation technique is exposure to a low-power NH/sub 3/ plasma prior to SiN deposition. Devices fabricated with the NH/sub 3/ treatment prior to SiN passivation show minimal gate lag and current collapse after extended dc bias operation. In addition, the rate of degradation of the microwave power output while under continuous microwave operation is improved by at least 100 times as compared to SiN passivated HEMTs that were not treated with the NH/sub 3/ plasma.     

60Co γ-rays irradiation effect in DC performance of AlGaN/GaN high electron mobility transistors

Unpassivated/passivated AlGaN/GaN high electron mobility transistors(HEMTs) were exposed to 1.25MeV60Co γ-rays at a dose of 1 Mrad(Si).The saturation drain current of the unpassivated devices decreased by 15%at 1 Mrad γ-dose,and the maximal transconductance decreased by 9.1% under the same condition;moreover,either forward or reverse gate bias current was significantly increased,while the threshold voltage is relatively unaffected.By sharp contrast,the passivated devices showed scarcely any change in saturation drain current and maximal transconductance at the same γ dose.Based on the differences between the passivated HEMTs and unpassivated HEMTs,adding the C-V measurement results,the obviously parameter degradation of the unpassivated AlGaN/GaN HEMTs is believed to be caused by the creation of electronegative surface state charges in source-gate spacer and gate-drain spacer at the low dose (1 Mrad).These results reveal that the passivation is effective in reducing the effects of surface state charges induced by the 60Co γ-rays irradiation.so the passivation is an effective reinforced approach.     

Correlation between surface-state density and impact ionizationphenomena in GaAs MESFET's

GaAs MESFET's passivated with PECVD SiN show a lower surface-state density in comparison with SiO passivated devices, as deduced from g _m(f) dispersion curves. Lower carrier multiplication due to impact ionization phenomena in the active channel and consequently a higher breakdown voltage are observed in SiO passivated samples. These effects are attributed to a lower peak electric field near the drain edge of the gate, deriving from an accumulation of negative surface charge     

Investigation of the impact of Al mole-fraction on the consequences of RF stress on Al/sub x/Ga/sub 1-x/N/GaN MODFETs

Variations of the low-frequency noise (LFN), power, and dc characteristics of a variety of SiN/sub x/ passivated AlGaN/GaN MODFETs with different values of Al mole-fraction, gate length, and gate drain spacing upon RF stress are investigated. It is experimentally evidenced that the variation of Al mole-fraction (x) of the barrier Al/sub x/Ga/sub 1-x/N layer from 0.2 to 0.4, has no considerable impact on the drain and gate low-frequency noise current characteristics. The most noticeable variation on the device characteristics upon long-term RF stressing has been on the pinch-off voltage. Although no material degradation by increasing the Al mole-fraction has been evidenced through the low-frequency noise data, it is observed that the variation of pinch-off voltage upon RF stressing becomes more important as the Al mole-fraction increases.     

High performance BCB-bridged AlGaAs/InGaAs power HFETs

A novel low-k benzocyclobutene (BCB) bridged and passivated layer for AlGaAs/InGaAs doped-channel power field effect transistors (FETs) with high reliability and linearity has been developed and characterized. In this study, we applied a low-k BCB-bridged interlayer to replace the conventional air-bridged process and the SiN/sub x/ passivation technology of the 1 mm-wide power device fabrication. This novel and easy technique demonstrates a low power gain degradation under a high input power swing, and exhibits an improved adjacent channel power ratio (ACPR) than those of the air-bridged one, due to its lower gate leakage current. The power gain degradation ratio of BCB-bridged devices under a high input power operation (P/sub in/ = 5 /spl sim/ 10 dBm) is 0.51 dB/dBm, and this value is 0.65 dB/dBm of the conventional air-bridged device. Furthermore, this novel technology has been qualified by using the 85-85 industrial specification (temperature = 85 C, humidity = 85%) for 500 h. These results demonstrate a robust doped-channel HFET power device with a BCB passivation and bridged technology of future power device applications.     

Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier Layers

The effect of SiN surface passivation by catalytic chemical vapor deposition (Cat-CVD) on Al/sub 0.4/Ga/sub 0.6/N-GaN heterostructure field-effect transistors (HFETs) was investigated. The channel sheet resistance was reduced by the passivation due to an increase in electron density, and the device characteristics of the thin-barrier HFETs were significantly improved by the reduction of source and drain resistances. The AlGaN(8 nm)-AlN(1.3 nm)-GaN HFET device with a source/drain distance of 3 /spl mu/m and a gate length of 1 /spl mu/m had a maximum drain current density of 0.83 A/mm at a gate bias of +1.5 V and an extrinsic maximum transconductance of 403 mS/mm. These results indicate the substantial potential of Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier layers.     

Impact of gate placement on RF power degradation in GaN high electron mobility transistors

We have investigated the RF power degradation of GaN high electron mobility transistors (HEMTs) with different gate placement in the source–drain gap. We found that devices with a centered gate show different degradation behavior from those with the gate placed closer to the source. In particular, centered gate devices degraded through a mechanism that has a similar signature as that responsible for high-voltage DC degradation in the OFF state and is likely driven by electric field. In contrast, offset gate devices under RF power stress showed a large increase in source resistance, which is not regularly observed in DC stress experiments. High-power pulsed stress tests suggest that the combination of high voltage and high current stress maybe the cause of RF power degradation in these offset-gate devices.     

Influence of layer structure on performance of AlGaN/GaN high electron mobility transistors before and after passivation

Intentionally undoped and three different, doped layer structures are used to investigate properties of AlGaN/GaN high electron mobility transistors (HEMTs) before and after SiN passivation. For unpassivated devices, the drain current, transconductance, cutoff frequency, and microwave output-power increase with increased doping level, in spite of an increase in the gate-leakage current. After passivation, an overall performance improvement of all devices occurs. The passivation-induced sheet charge decreases from 2×10¹² cm⁻² in undoped structures to ∼0.7×10¹² cm⁻² in higher doped structures and performance improvement with passivation is less pronounced for higher doped devices. However, the output power of unpassivated and passivated devices on higher doped structures is much higher than that on the undoped-passivated counter-part. These results underline an advantage of the doped layer structure for the preparation of high-performance AlGaN/GaN HEMTs.     

Current Collapse and High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Effect of surface passivation of AlGaN/GaN heterostructurefield-effect transistor

The effect of SiN passivation of the surface of AlGaN/GaN transistors is reported. Current deep level transient spectroscopy (DLTS) measurements were performed on the device before and after the passivation by a SiN film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device. The DLTS spectrum obtained from the measurement of the passivated device showed a significantly lower peak for this trap. The discrepancy in the DLTS peak amplitude is explained by the effect of the passivation on the surface traps and underlines the surface nature of the major defect noticed in the device     

AlN/GaN Insulated-Gate HFETs Using Cat-CVD SiN

The authors fabricated SiN/AlN/GaN metal–insulator–semiconductor heterostructure field-effect transistors (MIS-HFETs) using SiN passivation by catalytic chemical vapor deposition (Cat-CVD). Cat-CVD SiN increased the electron density of AlN/GaN HFETs by compensating the surface depletion of the two-dimensional electron gas. The MIS-HFETs had a maximum drain current density of 0.95 A/mm and a peak extrinsic transconductance of 211 mS/mm. A current-gain cutoff frequency of 107 GHz and maximum oscillation frequency of 171 GHz were obtained for the 60- and 70-nm-gate devices, respectively.     

高跨导AlGaN/GaN HFET器件研究

报道了蓝宝石衬底上AlGaN/GaNHFET的制备以及室温下器件的性能。器件栅长为0.8μm,源漏间距为3μm,得到器件的最大漏电流密度为0.7A/mm,最大跨导为242.4mS/mm,截止频率(fT)和最高振荡频率(fmax)分别为45GHz和100GHz。同时器件的脉冲测试结果显示,SiN钝化对大栅宽器件的电流崩塌效应不能彻底消除。     

Degradation mechanisms of GaAs PHEMTs in high humidity conditions

We have studied the degradation mechanisms of AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) under high humidity conditions (85 °C, 85% relative humidity). The degraded samples under high humidity conditions show a decrease in maximum drain current (I_max) and a positive shift in threshold voltage (V_th). Cross-sectional transmission electron microscopy (TEM) images from the deteriorated devices reveal an existence of damaged recess surface region and a peeling of a passivation film (SiN_x). The secondary ion mass spectrometry (SIMS) depth profile at the interface between the passivation film and AlGaAs surface also indicates the diffusion of gallium (Ga), arsenic (As) and aluminum (Al) into the passivation film. The degradation of PHEMTs arises from mainly two mechanisms: (1) the positive shift in V_th due to stress change under the gate caused by the peeling of passivation films, and (2) the decrease in I_max due to the net carrier concentration reduction of the AlGaAs carrier supply layer caused by the combination of surface degradation at the AlGaAs recess regions and diffusion of Ga, As and Al at the interface between the passivation film and AlGaAs surface. A special treatment just prior to the deposition of SiN_x films on the devices effectively suppresses the degradation of PHEMTs under high humidity conditions without degradation of the high frequency performance.     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.