A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-μm CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V_pp differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz±250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V_pp and up to 70 MHz with 0.7 V_pp. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply     

Analysis of band-to-band mixing distortion contributions in some usual circuit topologies

This paper uses hand analysis and a new fully numerical distortion contribution analysis technique to explain and optimize the nonlinear performance of analog circuits. Several example circuits are studied, where mixing of nonlinear distortion from one harmonic band to another is important. In some circuits the band-to-band mixing can be employed to reduce the overall distortion.     

A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs

A CMOS analog baseband transceiver with a 13-bit, 180 MSPS pipelined ADC and dual 12-bit, 180 MSPS current-steering DACs is presented. The ADC is implemented without a dedicated track-and-hold stage, utilizes a front-end 2.5-bit stage with matched MDAC/comparator tracking circuits, and demonstrates an ENOB of 10.6 bits at 15 MHz and 9.7 bits at 100 MHz, employing a low-jitter delay-lock loop for its phasing. The dual I/Q DACs show over 62 dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers     

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm 3.3V标准数字工艺实现.     

A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive readchannel

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-μm CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0     

A noble track-and-hold amplifier with 10-b 120-MS/s

A novel track-and-hold (T&H) employing an operational transconductance amplifier (OTA) with two cross-coupled differential pairs (CCDPs) is proposed for high-accuracy and high-frequency applications. The T&H has a simple architecture requiring smaller capacitors and fewer switches and offers higher speed, lower distortion and lower power dissipation than its op-amp-based counterparts. The chip implemented in 0.18 μm CMOS process operates from a single 1.8 V supply and achieves more than 10-bits precision for sampling rate in excess of 120 MS/s.     

A New Computer-Aided Method of Distortion Sensitivity-Analysis and Its Elimination Scheme for Power Electronic Circuits

A new general computer-aided algorithm for computing parameter sensitivities of distortion in power electronic circuits and its elimination scheme are proposed. The adjoint network approach is employed for calculating parameter sensitivities of the distortion factor and the ripple factor of current and voltage waveforms. An optimal filter design-algorithm to reduce undesirable harmonics is also proposed. Their performance is shown to be superior through demonstrated numerical examples.     

1-GHz GaAs ADC building blocks

GaAs ICs for high-speed, 6-b, 1G-sample/s (Gs/s) data acquisition are under development, using a low-cost conventional D-MESFET technology. First-generation sample-and-holds (S/Hs) and comparators are currently being sampled to customers. Diode-bridge and FET-switch S/Hs have been compared. Best performances have been achieved with diode-bridge switches: 1 ns and 6 bits. Comparators provide 6-b sensitivity at 1 GHz, but require offset adjustments. Second-generation analog-to-digital converter (ADC) building blocks have been made. Performances and applications of resulting circuits as well as advanced ADC design criteria are discussed, with special attention to yield. First results on a 4-b ADC are presented     

A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR

We discuss a design technique that makes possible the operation of track-and-hold (T/H) circuits with very low supply voltages, down to 0.5 V. A 0.5-V 1-Msps T/H circuit with a 60-dB SNDR is presented. The fully differential circuit is fabricated in the CMOS part of a 0.25-mum BiCMOS process, with standard 0.6-V V_T devices, and uses true low-voltage design techniques with no clock boosting and no voltage boosting. The T/H circuit has a measured current consumption of 600 muA     

Design of low distortion active inductor and its applications

This paper proposes a novel distortion reduction technique for active inductors. A bias current of a MOSFET, which acts as transconductor in an active inductor, is controlled to reduce a distortion of a active inductor. When an input voltage increases, the bias current is decreased by a control circuit. As a result of this control, transconductance of the MOSFET remains constant. An active inductor using this technique is free from distortion caused by a transconductance variation of a MOSFET. The proposed technique is applied to two different conventional active inductors and novel low distortion active inductors are derived. Computer simulations show that distortion of the proposed active inductor is very low. The proposed low distortion active inductors are applied to a second order bandpass filter and a voltage controlled oscillator. Thanks to the proposed technique, distortion of these circuits are reduced and their performance is improved.     

A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track-and-hold(T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits(ENOB) and 47.84 dB of the spurious free dynamic range(SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate;it achieves 5.48 bit of ENOB a...     

Performance Evaluation of a Novel Hybrid Multipulse Rectifier for Utility Interface of Power Electronic Converters

This paper presents an improved analysis of a novel programmable power-factor-corrected-based hybrid multipulse power rectifier (PFC-HMPR) for utility interface of power electronic converters. The proposed hybrid multipulse rectifier is composed of an ordinary three-phase six-pulse diode-bridge rectifier (Graetz bridge) with a parallel connection of single-phase switched converters in each three-phase rectifier leg. In this paper, the authors present a complete discussion about the controlled rectifiers' power contribution and also a complete analysis concerning the total harmonic distortion of current that can be achieved when the proposed converter operates as a conventional 12-pulse rectifier. The mathematical analysis presented in this paper corroborate, with detailed equations, the experimental results of two 6-kW prototypes implemented in a laboratory.     

Distortion In p-i-n Diode Control Circuits

Traditionally, distortion in p-i-n diodes has been thought to be only a function of the carrier lifetime and frequency of operation. This understanding is based on empirical evidence and is not entirely accurate. This paper will discuss the origins of p-i-n diode distortion and study the effects of various devices parameters on distortion performance. Included in the investigation on single-diode circuits will be switching circuits and reflective attenuators. In switch circuits, the analysis shows that distortion can be minimized by maximizing the stored-to-charge resistance ratio in the diode. In attenuators, the analysis shows that maximizing the i-region thickness will minimize distortion, independent of the device carrier life-time. In attenuators where multiple p-i-n diodes are used (the bridged-tee and PI are discussed), maximizing the i-region thickness also minimizes the distortion, independent of carrier lifetime. The model accurately predicts distortion signal cancellation in both single and multiple p-i-n diode circuits.     

Ku-band subsampling track-and-hold amplifier with 8 ENOB resolution

A wideband subsampling track-and-hold amplifier has been designed for input frequencies up to Ku-band and clock rates up to 2.5 GS/s. Circuits were fabricated in 1 /spl mu/m InP SHBT technology. Spur-free dynamic range measured with two-tone input frequencies of 12.6 and 12.602 GHz and a 2.5 GS/s clock rate ranges from 53-69 dB at an input level of -1 dBFS for each tone. Signal-to-noise ratio (SNR) test results show that the master/slave (M/S) track-and-hold design provides 59 dB of SNR in a 1 GHz bandwidth at input frequencies up to at least 2.6 GHz. A single track-and-hold dissipates 1.5 W while the M/S configuration dissipates 2.5 W.     

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

This paper describes a high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.     

基于Multisim的4种典型功放电路仿真研究

为了准确直观的理解4种典型功率放大电路的电路特性,文中研究了基于Multisim的功率放大电路的仿真测试。首先介绍了Multisim软件常用的分析方法。其次通过Multisim平台建立了4种功放电路的仿真模型,对其进行了瞬态分析和傅里叶分析。仿真结果表明,在基本型功放电路前端串接运算放大器可以提高电路稳定性,减小电路的交越失真。