Two-dimensional simulation of ferroelectric memory cells

An approach to increase the capabilities of integrated circuit nonvolatile memory is to take advantage of the hysteresis in the polarization of ferroelectric materials. For a rigorous analysis of the resulting devices, a suitable model for the ferroelectric effects has been developed. We present this model and show the results of its implementation into a device simulator. Although this model was designed especially for analysis of ferroelectric materials, it is also applicable to magnetic hysteresis phenomena     

Two-dimensional simulation of silicon avalanche cathodes

The characteristics of silicon avalanche cathode as a novel electron emitting device with ultra-shallow p-n junctions have been studied using the two-dimensional device simulator PISCES-IIB. The steady-state simulation indicates that the nonplanar surface topology resulting from fabrication process causes current crowding near the edge of the emitting area where the surface step exists. Current crowding degrades the emission uniformity and also reduces the emission current under increased reverse bias. The nonplanar surface structure also causes punchthrough in the epitaxial layer as the reverse bias on the cathode increases. As a result, the percentage of the cathode current contributing to emission decreases, reducing the emission efficiency consequently. The simulation shows that the portion of the cathode current that flows through the emitting area drops to as much as 30% at cathode bias higher than 12 V, compared to the same current just after breakdown. This also affects the rate of increase in the total emission current which is the product of the emission efficiency and the overall cathode current     

Two-dimensional avalanche simulation of collector-emitter breakdown

A two-dimensional (2-D) transient simulation approach with the avalanche effect included has been used to study breakdown phenomena in conventional vertical bipolar transistors of the n-p-n type. The simulated current responses to voltage ramps show the important difference in speed for the emitter-collector breakdown and collector-base breakdown. DC specified values may be too conservative     

Two-dimensional simulation of a high-voltage p-i-n diode with overhanging metallization

A two-dimensional computer simulation of a high-voltage p-i-n diode for a microstrip phase shift network mounted in parallel with a microstrip line has been carried out. The electric field distribution in four different device Structures has been analyzed. It is shown that the microstrip line which forms a metal overhang on top of the device can reduce its breakdown voltage due to enhanced total and normal field components at the silicon-dielectric interface. Also, this could lead to avalanche injection of hot carriers into the dielectric which could impair the long-term performance of the device. A structure which should prove less prone to these adverse effects is reported.     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

Two-dimensional simulation of orientation effects in self-alignedGaAs MESFETs

The stress-induced orientation effects in self-aligned GaAs MESFETs were studied using a two-dimensional analysis. Devices oriented along different crystal directions, with different gate lengths, and under different stress conditions were studied. It was found that the piezoelectric effect caused by the surface stress plays a very important role in the device characteristics of short-channel self-aligned MESFETs. Structure parameters such as lateral spreading of N⁺ ions and p-type impurity concentration in the substrate were found to have great influence on the short-channel effect as well as the orientation effect. The short-channel effects can be suppressed and the device performance improved if the devices are oriented in the right direction and the structure of the devices and the thickness of the surface dielectric layer are properly chosen     

Two-dimensional simulation for resonant tunneling transistor

A new two-dimensional device simulation for the resonant tunneling transistor is presented. In the simulation, the one-dimensional Schrodinger equation is solved for the intrinsic area of the transistor and the conventional two-dimensional drift-diffusion equations are solved for the extrinsic part. Both equations are coupled with the carrier generation-recombination term in the drift-diffusion equations. In addition, the Poisson equation is also solved self-consistently with them to take the charge distribution effect into account. The two-dimensional simulator has been successfully applied to the analysis of a resonant tunneling transistor and it was found that the current-voltage characteristics sensitively depend on the base resistance. This means that a two-dimensional treatment of the voltage drop in the base region is essential for an accurate simulation     

Two-dimensional self-consistent simulation of a triangular p-channel SOI nano-flash memory device

This paper presents the simulation of an SOI nano-flash memory device. The device is composed of a triangular quantum wire channel p-MOSFET with a self-aligned nano-floating gate embedded in the gate oxide. The simulation is carried out by combining TSUPREM-4 and a two-dimensional (2-D) self-consistent solution of the Poisson and Schrodinger equations. The fabrication process as well as quantum physics are taken into account. Hole distribution in the inversion layer of the triangular channel section is calculated in terms of wave functions and energy subbands. The threshold voltage shift between the programming and erasing of the device is investigated. In this paper, we show that the channel shape plays a crucial role in the programming voltage and the threshold voltage shift. Based on the fact that the holes are confined mainly at the top of the triangular channel section, we explain why our triangular channel device can be operated at relatively low programming voltage despite of a thick gate oxide and tunnel oxide. The threshold voltage shift in the triangular channel device is compared with that in a rectangular channel device. The result shows that the triangular channel device exhibits the larger threshold voltage shift.     

Two-dimensional computer simulation for switching a bipolar transistor out of saturation

A two-dimensional numerical analysis for the turnoff of a bipolar transistor from high injection level (VBE= 900 mV) is carried out. VBCis being kept constant at 1 V. Distributions of potential, electron, and hole density are interpreted and lead to a subdivision of the total transient time into four time regions, each governed by a single phenomenon. These phenomena are 1) fast discharge of the sidewall transistor, 2) the "lateral wave" which has the dominating influence in the total switching time, 3) the vertical discharge, and 4) the emitter discharge. The transient behavior is essentially ruled by two-dimensional lateral effects. Hence one-dimensional models are not adequate for switching a transistor out of saturation.     

Two-dimensional simulation of laser diodes in the steady state

A fully self-consistent steady-state two dimensional model of laser diodes is presented. The model consists of the simultaneous solution of the Poisson and the electron and hole drift-diffusion equations, the wave equation, and the photon rate equation. Excellent agreement with experiment is obtained for both gain-guided and index-guided laser diodes. Specific results are given for channeled-substrate planar (CSP) lasers. It is shown that comparable electron current confinement is provided by both internal strips (p-GaAs barriers) and zinc-diffused planar stripes. The confinement in the first case is due to energy barriers and in the latter case is due to lateral electric fields. For the holes, current spreading is shown to be reduced substantially for the planar stripes because of the use of high-resistivity n-cap layers. It is demonstrated that the thickness of the p-GaAs layers can be smaller than the minority carrier diffusion length since only a very small fraction of the laser light passes through the barriers     

Two-dimensional quantum mechanical simulation of chargedistribution in silicon MOSFETs

A solver for the two-dimensional (2-D) Schrodinger equation based on the k-space representation of the solution has been developed and applied to the simulation of 2-D electrostatic quantum effects in nano-scale MOS transistors. This paper presents the mathematical framework of the simulator, addresses the related accuracy and efficiency problems, and discusses the simulations performed to validate it. Furthermore, the 2-D quantum effects observed in the simulation of charge densities in tens-hundreds nanometer scale MOS structures are described     

Design of a micromachined thermal accelerometer: thermal simulation and experimental results

This paper describes numerical simulation of a micromachined thermal accelerometer and experimental measurements. The sensor principle consists of a heating resistor, which creates a symmetrical temperature profile, and two temperature detectors symmetrically placed on both sides of the heater. When an acceleration is applied, the free convection is modified, the temperature profile becomes asymmetric and the two detectors measure the differential temperature. This temperature profile and sensor sensitivity according to the distance heater-detector have been studied using numerical resolution of fluid dynamics equations with the commercial code CFD2000/STORM: it shows that the optimum distance between the temperature detectors and the heater is about 300 μm. A thermal accelerometer with 3 pairs of detectors placed at 100, 300 and 500 μm from the heater was manufactured using the techniques of micromachining silicon and experimental measurements have shown a good agreement with the numerical simulations: the experimental optimum distance between heater and detectors seems to be close to 400 μm and the differential temperature of detectors is about 3 °C/g for an operating heater power of 54 mW and an heater temperature rise ΔT of 238 °C. The electrical sensitivity is then 2.5 mV/g.     

Comparison of thermal runaway limits under different test conditions based on a 4.5 kV IGBT

This investigation focuses on determining the temperature-dependent leakage current limits which compromise the blocking safe operating area for silicon IGBT technologies. A discussion of a proper characterization method for selecting the maximum rated junction temperature for devices operating at high temperatures is given by comparing the different testing methods: Static performance (including and excluding self-heating effects), Short Circuit Safe Operating area and High-Temperature Reverse Bias. Additionally, a thermal model is used to predict the junction temperature at which thermal runaway takes place. In this paper guidelines are proposed based on the correlation among short circuit withstand capability and off-state leakage current for guarantying reliable operation and ensuring that they are thermally stable under parameter variations. This study is helpful to facilitate application engineers for defining the correct stability criteria and/or margins in respect of thermal runaway.     

Two-dimensional Monte Carlo simulation of a submicron GaAs MESFET with a nonuniformly doped channel

A two-dimensional-ensemble Monte Carlo program coupled with a program for solving Poisson's equation is used to perform a self-consistent simulation of a GaAs MESFET having a nonuniformly doped (ion-implanted) channel. For V_gs = ?0.5 V and V_ds = 1 V, the simulation yields I_ds = 18 mA/50 μm, g_m = 755 mS/mm and f_T = 230 GHz. The results are compared to those obtained from a conventional 2D device-analysis program which uses static velocity-field characteristics and an empirical expression for low-field mobility versus doping concentration. The currents, transconductance, and cutoff frequency obtained from the Monte Carlo simulation are considerably larger than those obtained from the conventional 2D analysis. This difference is explained by the fact that the conventional device analysis program fails to account for transient transport phenomena.     

Two-dimensional simulation of constricted-mesa InGaAsP/InPburied-heterostructure lasers

A fully two-dimensional self-consistent numerical model of the steady-state behavior of 1.3 μm constricted-mesa InGaAsP/InP buried-heterostructure lasers is presented. Devices operating at this wavelength are very temperature sensitive and therefore the model for the first time includes coupled solutions to the thermal as well as the electrical and optical equation sets. The temperature dependence is included in the Fermi-Dirac statistics, bandgaps, mobilities, densities of states, Auger recombination coefficients, intervalence band absorption, optical gain, and thermal conductivities. The lasing mode profiles, carrier distributions, threshold currents, and temperature characteristics are analyzed and good agreement is found with experimental results, including the temperature dependence of the threshold current and the prediction of a break-point temperature. The optimum design parameters are investigated for reduced threshold currents, and the effect of optical loss in the blocking regions on lateral-mode control is analyzed     

Modeling of temperature profile,thermal runaway and hot spot in thin film solar cells

Hot spot and thermal runaway are serious phenomena leading to the degradation of CdTe thin film solar cells. Here, we show that these issues are well related to temperature variation in the device structures mostly because of current flowing across transparent conducting oxide (TCO) layer or back contact of a CdTe device structure: glass/TCO/CdS/CdTe/graphene. Graphene nanolayer was chosen as the back contact because of its high thermal conductivity. We present a modeling of the temperature profile in CdTe thin film devices considering both uniform and nonuniform temperature distribution and current flowing across TCO layer. Temperature profile for hot spots at the edges of devices are modeled and compared to literature reports of both modelled and measured data. The model is based on the heat transfer equation (which uses thermal resistances) and in particular accounts for convection and conduction resistances by means of their ratio, the Biot number – a factor that could be optimized in the design of photovoltaic devices. Profiles were modelled taking into account both uniform and non-uniform temperature profiles for the glass, and currents flowing though the TCO. It is shown that the current flowing across the TCO layer can contribute to thermal runaway and its spreading to neighbouring areas. Overall the modelling data suggests that thin film solar devices could be designed to minimise hot spot runaway issues by taking into account the thickness and temperature dependence of the layers thermal conductivity, convection and conduction resistances. This can be extended to other solar cell structures or large scale modules.     

Two-dimensional simulation of conducted currents characteristics inelectrical discharges

In this paper, a simple general electrical discharges circuit model for electrical discharge current waveform simulation in overvoltaged air gaps is presented. A macroscopic circuital method of simulation utilizing the standard SPICE network simulator, based on a two-dimensional (2-D) nonlinear impedances network has been proposed. The structure of the simulation framework is designed to take into account the electrode geometries in a straightforward way. A study of conducted current waveform for different electrode geometries has been done. Experimental data have been used to validate the simulation results     

Two-dimensional computer simulation of the breakdown characteristics of a multi-element avalanche photodiode array

A two-dimensional computer simulation of the breakdown characteristics of a silicon multi-element avalanche photodiode array has been carried out. The effect of the interaction of the depletion layers of two adjacent avalanche photo diode (APD) elements on the breakdown voltage of the multi-element array has been modeled. The influence of the various physical parameters of the device on its breakdown voltage is investigated. Five different device structures are considered. Design guidelines for realizing true bulk breakdown in the device are presented. With the aid of these two-dimensional computer simulation results, the effect of scaling down the device dimensions, in an effort to increase the packing density of the device, on its breakdown voltage is also outlined.     

Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10~(12) cm~(-2),an implant ...     

四管CMOS图像传感器中像素图像拖影的二维仿真与优化

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 10¹² cm^–2, an implant tilt of –2^o, a transfer gate channel doping dose of 3.0 × 10¹² cm^-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.