Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level.     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.     

Three dimensional devices fabricated by silicon epitaxial lateral overgrowth

Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon over oxide are used for novel device technologies in CMOS and bipolar with a large potential for BICMOS. A stacked inverted P-MOS device in crystalline Si on top of an oxidized poly-gate was fabricated with the critical “as-grown” interface state densities, between the ELO silicon grown over the existing poly-oxide, measured to be less than 2 × 10¹¹/ (cm²-eV) near midgap. A SiH₂Cl₂-HCl-H₂ in a LPCVD epitaxial system was employed at 150 Torr and at 900° C to produce the ELO/SEG material. The initial stacked-inverted 3D P-MOS devices typically show hole mobilities of greater than 160 cm²/V-s with adequate subthreshold characteristics for 3-dimensional CMOS implementation. A new form of SEG was used to grow single crystal silicon horizontally between dielectric walls to form SOI material in thin slabs, called confined lateral selective epitaxial growth (CLSEG). BJT-SOI device structures with β_dc > 150 were fabricated in CLSEG silicon to demonstrate the device quality material and to show the 3D-SOI capability.     

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C-V and I-V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

亚0.1μm高K栅介质MOSFETs的特性

用二维模拟软件 ISE研究了典型的 70 nm高 K介质 MOSFETs的短沟性能 .结果表明 ,由于 FIBL 效应 ,随着栅介质介电常数的增大 ,阈值电区减小 ,而漏电流和亚阈值摆幅增大 ,导致器件短沟性能退化 .这种退化可以通过改变侧墙材料来抑制     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness t_si were evaluated for 20–100 nm channel length. The source region was found to merge at pillar thickness below 75 nm, which results in floating body effect and creates isolated region in the middle of pillar. The vertical devices using ORI method show better performance than those with conventional implantation method for all pillar thickness, due to the elimination of corner effect that degrades the gate control. The presence of isolated depletion region in the middle of pillar at floating body increases parasitic effect for higher drain potential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device.     

Electrical method of measuring physical thickness and nitrogen concentration of silicon oxynitride gate dielectric for MOSFETs

This paper proposes an electrical method of measuring the physical thickness T_ox and the nitrogen concentration α_N of the silicon oxynitride (SiON) gate dielectric for MOSFETs. The proposed method uses the facts that the gate dielectric breakdown field strength E_BD depends on α_N for a given T_ox and the direct tunneling (DT) current depends strongly on T_ox. Gate current I_g versus gate voltage V_g (I_g-V_g) curves at a given α_N were calculated for different T_oxs using the DT model, and measurements were compared to the curves to obtain T_ox. The α_N was obtained by comparing the measured E_BD at a given T_ox with the theoretical E_BD for a SiON gate dielectric. These two steps were iterated until the convergence error of α_N was less than 1%. The I_g-V_g curves calculated using the extracted T_oxs and α_Ns agreed very well with measurements when V_g was less than the gate breakdown voltage. The difference between the equivalent oxide thickness (EOT) measured using the C-V method and the EOT calculated using the extracted T_ox and α_N was less than 7%, demonstrating that the proposed method can accurately determine T_ox and α_N of an ultra-thin SiON gate dielectric from only the measured I_g-V_g curve of the MOSFET.     

非对称异质双栅应变硅MOSFETs 二维模型研究

基于对二维泊松方程的精确求解,本文对全耗尽型非对称异质双栅应变硅MOSFET的二维表面势,表面电场,阈值电压进行了研究。模型结果和二维数值模拟器的结果很吻合。此外并对该器件的物理作了深入的研究。该模型对设计全耗尽型非对称异质双栅应变硅MOSFET器件有着重要的指导作用.     

Study of the laser-recrystallized film with a control of grain boundary location by using surrounding antireflection cap method

A modified technique for unseeded laser-recrystallization of poly-crystalline silicon films deposited on amorphous insulators has been developed whereby grain boundary location in the recrystallized silicon film can be controlled. In this technique, the silicon film is encapsulated with an antireflection cap with windows and then recrystallized by cw-Ar ion laser irradiation. Grain boundaries are removed from the silicon film at the place where the window is opened because of a temperature gradient due to a change in laserbeam absorption in the silicon film. The (100) texture is observed in the grain-boundary-free areas although the silicon shows (110) texture before the recrystallization. An SOI/ MOSFET has been fabricated in the recrystallized film. The channel regions of MOS-FET’s are aligned in the window regions. Field-effect mobility of 490 cm²/Vs is obtained for n-channel MOSFET’s. Source-to-drain leakage current of 5fA/μm is obtained at drain voltage of 5V and back-gate voltage of -100V for the W/L = 10 μ/2 μm MOSFET.     

漂移区阶梯掺杂的双栅SOI LDMOS研究

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.     

双层复合有机栅绝缘膜漏电机理的研究

本文研究了利用旋涂法在硅衬底上制备的聚甲基丙烯酸甲酯(PMMA)和三氟乙烯-偏氟乙烯的共聚物(P(VDFTrFE))双层复合绝缘膜的漏电机理,采用这种膜的MIS器件的单位面积电容为32nF/cm2。电流-电压测试结果显示在不同的电压范围内其漏电曲线出现转折点,反映了这种膜在不同的电场下有不同的漏电机制。对实验结果拟合分析表明,在0~1V电压范围内,其漏电主要是Poole-Frenkel机制控制;在1~25V电压范围内,主要是以肖特基发射电流为主;而在35~40V的电压范围内,绝缘膜漏电流是空间电荷限制电流。     

A new double gate SOI LDMOS with a step doping profile in the drift region

uences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOILDMOS.     

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.     

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.     

简单逻辑门电路学习方法初探

逻辑门是集成电路上的基本组件,逻辑门电路是当前数字电路广泛应用的重要前提和基础,它是不单是物理教育的重要组成部分,更是电子电器和计算机等相关专业的基础知识。由于逻辑电路要领功能繁多,记忆复杂,不易于掌握,学习起来容易感到力不从心。本文介绍了逻辑门电路的基本概念及表示方法,用类比的方法对逻辑门电路的规律进行总结,最后重点阐述逻辑门电路的实际应用。