Room-Temperature p-n-p AlGaAsSb–InGaAsSb Heterojunction Phototransistors With Cutoff Wavelength at 2.5 $mu$ m

Novel p-n-p AlGaAsSb-InGaAsSb heterojunction phototransistors (HPTs) grown by solid-source molecular beam epitaxy have been proposed and demonstrated. The p-n-p phototransistor structure provides a higher emitter injection ratio than its n-p-n counterpart, due to the large conduction band offset and almost continuous valence band edges between InGaAsSb and AlGaAsSb quaternary alloys. The resulting HPT devices exhibit high responsivities under a bias voltage above 0.3 V. A high room-temperature spectral responsivity of 2984 A/W is achieved at 2.24 mum, corresponding to an optical gain of 1652. The 50% cutoff wavelength of spectral photoresponse at room temperature is 2.50 mum. A room-temperature specific detectivity (D^*) of 8.3times10 ¹¹ cm middot Hz^1/2/W is obtained     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

Design techniques for IC voltage regulators without p-n-p transistors

Design techniques for IC voltage regulators without p-n-p transistors are discussed. Included is a brief discussion of the problems associated with p-n-p transistors that can be used as shunt devices in voltage regulators, as well as two methods for eliminating the p-n-p shunt device that is commonly used in regulators. The first method applies to nontemperature-compensated voltage regulators. It is a method of reducing the sensitivity of regulators to changes in power supply, using a phi cancellation technique instead of a p-n-p shunt device. This method greatly improves regulator voltage tracking. The second method is a method of eliminating the p-n-p transistor in a temperature-compensated bandgap-referenced voltage regulator using a differential amplifier to maintain current equality in tracking transistors. It is shown that the elimination of the p-n-p device will add a higher degree of design freedom while decreasing the susceptibility of the design to process variations.     

A new lateral MOS-controlled thyristor

A lateral MOS-controlled thyristor (LMCT) structure that uses an MOS gate to turn it both on and off is presented. The device structure offers improved maximum turn-off current capability and forward voltage drop. The former is achieved by using a DMOS transistor and a parasitic vertical p-n-p transistor, while the latter is achieved by eliminating a parasitic lateral p-n-p transistor in the conventional structure. The device utilizes the resurf technique to achieve high area efficiency, breakdown voltage, and reliability. Devices that have more than 250-V forward blocking capability were fabricated in dielectrically isolated silicon tubs using the standard bipolar-CMOS-DMOS process     

An investigation of the sensitivity of lateral magnetotransistors

An investigation of the magnetic-field sensitivity of lateral, double base contact p-n-p magnetotransistor is reported. At very low collector current levels the sensitivity is an exponential function of the base current and rises up to 30 A/A.T at 1 T. At larger collector currents sensitivity decreases drastically and approaches the usual value of less then 1.5 A/A.T. This behaviour is explained in terms of a Hall-type voltage, which is generated in the base region and causes a magnetic-field-modulated injection of carriers.     

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.     

New insulated-gate thyristor structure with MOSFET coupled baseregions

A new insulated-gate thyristor (IGTH) structure in which the base of n-p-n transistor is coupled to the base of p-n-p transistor through a MOSFET is described for the first time, In the new structure, called base coupled insulated gate thyristor (BC-IGTH), the parasitic lateral p-n-p carrier injection inherent in previously reported thyristor structures such as the MCT, BRT, and IGTH is absent. The absence of parasitic lateral p-n-p carrier injection results in low on state voltage drop and high controllable current capability for this structure. The turn-on process in the new structure is fundamentally different from other MOS-gated thyristor structures in that in the new structure, the higher gain n-p-n transistor is turned-on first, which then provides the base drive for the lower gain p-n-p transistor. Multicellular 800 V devices of the new thyristor structure were fabricated using a double-diffused DMOS process, and were found to give on-state drop of 1.1 V at 200 A/cm², and controllable currents in excess of 100 A/cm² were obtained by forming MOS-gate controlled emitter-to-base resistive shorts     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-$muhboxm$CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5$hboxppm/^circhboxC$from 0$^circhboxC$to 100$~^circhboxC$. With a 0.9-V supply voltage, the measured power noise rejection ratio is$-hbox25.5~hboxdB$at 10 kHz.     

An optronic negative resistance circuit

A negative-resistance circuit has been constructed with the combination of a p-n-p junction transistor, a light emitting p-n diode and a n-p-n photo transistor. The circuit provides negative-resistance voltage-current characteristics in both for increasing and decreasing the positively applied voltage, and holds a facility to obtain external control optically. The breakover voltage can be set at a desired value according to the adjustment of bias resistances for the p-n-p junction transistor.     

A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a1-Vp-p range

This paper describes the design and measured results of an all-n-p-n low-voltage (2.5 V), low-current (1 mA), large-swing (1 V_p-p), low-distortion (-53 dB, 1 V_p-p) active filter using a conventional bipolar process. The transconductors for the filter are composed of Gilbert cell transconductors. Distortion has been improved by feedback circuits without increasing the supply voltage and without using p-n-p transistors. The filter is a gyrator-capacitor type third-order Butterworth low-pass filter with a nominal cutoff frequency of 192 kHz. A voltage scaling technique has been applied directly to the gyrator-capacitor filter. This has improved the signal-to-noise ratio by 3 dB. Simulation results indicated that a fast operation up to tens of MHz is possible with a standard bipolar process, as the signal path is composed only of n-p-n transistors     

The design and optimization of high-performance, double-polyself-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p⁺ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (⩾40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits     

The early voltage of a bipolar transistor

A simple concentration profile is assumed and the Early voltage of a p-n-p transistor is calculated. The base gradient, the current gain, and the collector resistivity appear as parameters in the final equation for the Early voltage. Experimental results are presented.     

Indirect current feedback instrumentation amplifier with acommon-mode input range that includes the negative roll

An instrumentation amplifier which can handle common-mode voltages that extend 200 mV below the negative supply is presented. The extended range is combined with a common-mode rejection of 92 dB and an accuracy of 0.1%, without the need for on-chip trimming. This has been achieved by the use of two p-n-p V-to-f converters in an indirect current feedback configuration. The output voltage can reach the negative supply. The offset voltage is 0.3 mV, and the noise voltage is 30 nV/√Hz. The circuit operates at supply voltages down to 2.5 V, and the quiescent current is 240 μA. The instrumentation amplifier has been integrated in a semicustom bipolar process     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs     

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.     

一种新型的电流模式曲率补偿带隙基准源

提出了一种新型的低压带隙基准源,与传统的带隙基准不同,该电路引入了第三个电流,以消除双极型晶体管射基电压的温度非线性项,从而实现曲率补偿。采用0．18μmCMOS工艺进行设计验证,HSpice仿真结果表明,室温下的输出电压为623mV,-55～＋125℃范围内的温度系数为4．2ppm／℃,1．0～2．1V之间的电源调整率为0．9mV／V。     

Beta measurement and beta requirement in I/SUP 2/L gates

A new approach to beta measurement in the inversely operated I/SUP 2/L transistor is described, one that avoids arbitrary definitions and terminal-condition specifications. The authors deactivate the lateral p-n-p by symmetrical biasing so that direct measurement of n-p-n base current becomes possible. Further measurements demonstrate the validity of this approach, and also determine the beta necessary for a desired saturation voltage.     

A high speed 16 kbit ECL RAM

A 16384 /spl times/ 1 bit ECL RAM (emitter coupled logic random access memory) with an access time of 15 ns and a power dissipation of 700 mW has been developed. The high packing density and performance were achieved by using a p-n-p load cell, a novel ECL circuit, and U-groove isolation. The test results proved that a p-n-p load cell is very effective in producing a fast high-density bipolar RAM having a capacity of over 64 Kbits.     

A delay model and optimization method of a low-power BiCMOS logiccircuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage