新颖的教学用稳压电源的设计

根据职业教学用稳压电源的特点,通过分析低功耗稳压集成电路,采用TL431集成电路的比较特性,实现三段式输入电压自动调节以提高电源效率.设计了符合职教实验电源要求的低功耗,高性价比的教学用稳压电源.     

新颖的教学用稳压电源的设计

根据职业教学用稳压电源的特点,通过分析低功耗稳压集成电路,采用TL431集成电路的比较特性,实现三段式输入电压自动调节以提高电源效率。设计了符合职教实验电源要求的低功耗,高性价比的教学用稳压电源。     

An IC medium power voltage regulator

This article describes a monolithic integrated-circuit voltage regulator for use in medium-power applications in the achievement of ``local' or ``on-card' regulation. Included are design features, an explanation of circuit's operation, a dc analysis, regulation analysis, performance characteristics, design rules and considerations, and selected applications.     

A family of PFC voltage regulator configurations with reducedredundant power processing

This paper discusses a systematic method for deriving basic converter configurations that achieve power factor correction (PFC) and voltage regulation. The discussion begins with a general three-port representation of power supplies that provide PFC and voltage regulation. Based on this representation and a power flow consideration, a systematic procedure is derived to generate all possible minimal configurations. Among these configurations, only a few have been known previously and used in practice. It is found that the efficiency of PFC voltage regulators can be improved by reducing the amount of redundant power to be processed by the constituent converters. A systematic circuit synthesis procedure is proposed for creating PFC voltage regulators with reduced redundant power processing. Experimental measurements verify the improved efficiency     

A novel ac-ac buck-boost voltage regulator with unity input power factor

This paper describes the design and control of a novel ac-ac buck-boost converter. In this new configuration, an ac-to-ac converter is connected between the ac mains and the load to provide regulated ac output voltage. Two topologies of the ac-to-ac converter are suggested and the current controller strategy is presented. The new regulator has nearly unity input power factor for a change in the load voltage from 10% to more than 200% of the supply voltage. The four-quadrant operation of the proposed controller enables it to accept reactive loads. Theoretical analysis and practical controller implementation using the DSP controller board are presented.     

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.     

一种低功耗宽频带LDO线性稳压电路设计

设计了一种用HHNEC0.35μmBCD工艺实现的LDO线性稳压器,该LDO是一款低功耗,带宽大的低压差线性稳压器。对其结构和工作原理进行分析,讨论了关键电路的设计,模拟结果验证了设计的正确性。     

A microwatt switched-capacitor voltage doubler-based voltage regulator for ultra-low power energy harvesting systems

This paper presents an SC voltage doubler-based voltage regulator for ultra-low power energy harvesting applications. It produces a stable 1.2-V power supply, using inputs from 0.63 to 1.8 V. External compensation and an on-chip output capacitor ensure good performance even with zero load current and any load capacitance. The regulator tolerates arbitrary input ramp-ups, and is immune to blackout and brownout. A stability analysis for the regulator control loop is presented. The regulator ASIC is implemented in a 180 nm CMOS process. The measured regulator peak power and current efficiency are 63 and 49 %, respectively. The performance has been characterized with load currents from zero to \(100\,\upmu\)A.     

On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique

We propose a NMOS low drop-out voltage regulator suitable for on-chip power management. The circuit does not requires any external components for achieving compensation since it is internally compensated. A dynamic biasing strategy and a clock booster allows to properly drive the NMOS power transistor in a power efficient fashion and without limiting the speed response of the regulator. Transistor level simulations confirm the effectiveness of the proposed approach.     

Design of a low power voltage regulator for high dynamic range of load current

This paper presents a design technique of a low power, linear voltage regulator for high dynamic range of load current with good transient performances. It has been achieved by introducing a dynamic leakage path (pull down) at the driver stage of the voltage regulator. The pull down current through the dynamic leakage path is kept very small in steady condition for minimizing internal static power. While in high-to-low load current transition, the current through the dynamic leakage path is magnified for a small duration of time to achieve smaller settling time. The concept of the dynamic leakage path proves to be a more power efficient method than the static leakage method, especially in low standby current applications. The circuit is implemented in 0.18?µ CMOS technology and the voltage regulator generates 1.9?V from 3.3?V supply. The dynamic leakage path consumes additional 37?µA current, averaged over 7.2?µS time when the load current switches from high to low value, but consumes only 14?µA current in steady state.     

A bi-channel voltage regulator protecting smart cards against power analysis attacks

The bi-channel voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It generates the internal power supply voltage from the external power supply voltage provided by card readers, while ensuring the uncorrelation between the external power supply current and the internal power supply current. The power supply current of an electronic system can be decomposed into a DC component, which contains little information, and an AC component, which handles considerably more. In order to reach a good compromise between regulation and security, while respecting the smart card stringent technological constraints, these two components are treated separately by a bi-channel power structure. The presented implementation has been simulated from the process parameters of a STMicroelectronics 0.18 \upmum0.18\,\upmu\hbox{m} CMOS technology. It provides a 1.8 V output voltage from a 2 to 5.5 V input voltage range. The structure has been sized to handle a 25 mA DC current while hiding a 20 MHz AC current presenting 75 mA peaks. Its estimated area is approximatively 0.8 mm²0.8\,\hbox{mm}^2.     

Analysis and design of a low power regulator for a fully integrated HF-band passive RFID tag IC

We present a design for a low-dropout regulator suitable for use as a radio-frequency identification (RFID) tag IC that offers low power consumption while accommodating large load current variations using a small on-chip storage capacitor. Because of the low power design constraint, both the input and output impedances of the embedded current buffer are included for regulator stability analysis. A damping factor control technique is employed to ensure stability for the regulator with a small on-chip capacitor. Our analysis shows that the regulator provides a phase margin of greater than 45° over the full load current variation from 1 to 500 μA. Measurements show that the output voltage variation is less than 110 mV when the input voltage changes from 2.5 to 4 V under the same conditions of load current change, which indicates that the performance of the regulator is suitable for the RFID tag IC. The regulator consumes 10 μA of current and generates a nominal output of 1.8 V. The regulator design technique was successfully implemented in a fully-integrated HF-band passive RFID tag IC that satisfies the ISO-14443 type-B protocol. The tag chip is fabricated in a 1-poly 6-metal low-power 0.18 μm CMOS technology with a CoSi₂-Schottky diode and EEPROM process.     

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1 MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 μs, at full load transition. The total ground current including the bandgap reference circuit is 28 μA and the active chip area measures 290 μm × 360 μm in a 0.18 μm CMOS technology.     

一种脉冲调宽式电压调节器的研制

介绍了UC3637双PWM控制器的组成及其特点。在此基础上提出了一种应用该控制器设计航空交流发电机调压器的方法,并给出了具体的硬件电路。新研制的调压器不仅具有结构简单、实用、可扩展性好的特点,而且抗干扰能力强,调压精度高。     

用降压稳压器获取高电压

几家半导体制造商所提供的电流型降压控制器的输入电压范围是30～36V,但输出电压范围只能从基准电压到大约6V;这种输出电压的局限性是电流检测放大器的共模电压限制引起的.在实际应用中,电源设计师必定能为打印机、服务器、路由器、网络设备和测试设备产生很高的输出电压.采用常规降压稳压器来提供较高的电压是一个难题.图1所示电路可解决这个难题:采用一个外部运算放大器、一个小信号pnp三极管和一个低输出电压降压稳压器,在负载电流高达2.5A时通过27V输入电源提供了20V输出电压.     

A low power CMOS voltage reference generator with temperature and process compensation

A low power CMOS voltage reference with process compensation is presented in TSMC 0.18-μm standard CMOS technology. Detailed analysis of the process compensation technique is discussed. The circuit is simulated with Spectre. Simulation results show that, without any trimming procedure, the output voltage achieves a maximum deviation of 0.35 % across different process corners. The temperature coefficient of the proposed circuit is 12.7 ppm/°C in a temperature range from ?40 to 85 °C and the line sensitivity is 0.036 mV/V with a supply voltage range from 1.2 to 2.5 V under typical condition. The maximum supply current is 390.4 nA at maximum supply voltage and ?40 °C. The power supply rejection ratio is ?68.3 dB at 100 Hz and 2.5 V without any filtering capacitor.     

FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.     

A supply-noise-insensitive CMOS PLL with a voltage regulator usingDC-DC capacitive converter

A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-μm 3.3-V standard digital CMOS process and occupies 2.3 mm². The power consumption at 3.3 V including buffer is 42 mW at 500 MHz     

Broadband beamforming with power complementary filters

This paper addresses the design of broadband finite impulse response (FIR) beamformers with a power complementarity property. The power complementarity requirement is needed to preserve the whiteness of the channel noise at the beamformer output, which allows the application of optimum trellis-based equalizers to the output signal. The power complementarity property imposes non-negative definite quadratic constraints on the beamforming filters so that the beamformer design is expressed as a constrained quadratic optimization problem. Two approaches are proposed to solve this problem. The first method is a Lagrangian relaxation technique, which exploits the fact that the dual mathematical problem reduces to the unconstrained minimization of a convex function over a convex domain. A second approach employs a cascaded lattice representation of the power complementary filterbank and performs the beamformer design incrementally, one lattice stage at a time     

基于可调式稳压器LM317的直流稳压电源

该设计主要利用可调式稳压器LM317实现直流稳压电源的正负输出可调性。整个电源主要由变压器、整流电路、滤波电路,以及稳压电路几部分组成。其体积小,稳定性好且性价比较高。主要介绍其具体实现及原理,并分析具体硬件电路的工作原理及具体实现方法。结合单片机原理以及其他相关集成电路模块的相关原理实现了直流稳压电源的显示等具体功能。经反复实验,结果表明其具有灵活的可调性,控制效果良好。该电源可广泛运用于电力电子、仪表、控制等实验场合。