Frequency Domain Analysis of Transmission Zeroes on High-Speed Interconnects in the Presence of an Orthogonal Metal Grid Underlayer

This paper addresses the topic of high-speed interconnects in high density systems [systems on chip (SoCs), systems in package (SiPs), systems on package (SoPs), and multichip modules (MCMs)]. These microstrip or coplanar lines have, often, an underlayer of orthogonal metal grids liable to affect transmission characteristics. The characterization proposed in this paper relies on $S$-parameter measurements and electromagnetic simulations. The grids under study are of two kinds: grounded (CC) and floating (CO). In both cases, the signal is distorted in the time domain further to the occurrence of transmission zeroes whose position depend mainly on the grid length and, of course, on the grid charge, i.e., CC or CO. In order to easily estimate this position, we developed a simple equivalent circuit model and validated it by measurements and electromagnetic simulations. Then it was used to develop a set of expressions enabling one to analytically pinpoint the location of transmission zeroes in the frequency domain, while remaining valid for any underlayer of orthogonal metal lines or grids.      

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

网孔状地参考面上高速互连的信号完整性分析

本文主要基于实验研究,并结合三维全波电磁和电路系统仿真在频域和时域对高速多层PCB板中网孔状接地层或电源层上高速互连的信号完整性性能进行了测试和仿真分析,并对网孔状地参考面的周期性结构所呈现的频率带通(带阻)特性进行了理论分析.指出,参考面中的网孔会对跨越网孔的信号线传输特性产生较大扰动,甚至在信号频谱范围内产生局部的阻带,影响高速信号传播.最后,给出了网孔状地参考面高速互连的设计规则.     

Study of the DC biasing effect on insertion losses in high-frequency interconnections

The paper deals with an experimental investigation of the behavior of high-frequency Si/SiO₂/Al based interconnects when an extra DC bias voltage is applied, by means of which the conductor line changes the surface properties of the semiconductor substrate. By superposing a DC bias to the high-speed signal applied to the line, the insertion losses caused by the semiconductor substrate show a significant decrease over the observed frequency range. In order to study this effect a number of test samples containing several microstrip asymmetric transmission lines were prepared and measured. The obtained results suggest a way of controlling the performance and energy propagation of interconnects on semiconductor substrates. The observed effect can be successfully applied in high-speed blocks with tunable parameters.     

Characterization of micromachined transitions for high-speedintegrated packages

Micromachined transitions are characterized with abrupt and taper dielectric and conductor discontinuities. Constant impedance designs are studied for interconnects printed on the same substrate that traverse two different substrate heights. The best transition, when compared to the constant height design, has better than 20 dB return loss over 40 GHz. Its effective dielectric constant variation is less than 0.25 dB across the bandwidth, which indicates a low dispersion interconnect design with a micromachined transition     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

Efficient computation of frequency-dependent parameters for on-chipinterconnects via two-dimensional FDTD and time signal predictiontechnique

An efficient two-dimensional finite difference time domain (2-D-FDTD) method combined with time signal prediction technique has been proposed for the frequency-dependent parameters computation of on-chip interconnects in high-speed integrated circuits (ICs). A graded mesh algorithm and lossy absorbing boundary condition are proposed and adopted in the 2-D FDTD analysis to reduce the number of spatial grid points in the simulation region. The introduction of time signal prediction technique to predict the future signal in the time domain or extract the parameters in the frequency domain of uniform transmission lines reduces the computation time drastically. With these, the substrate and conductor losses are both included in one analysis. This algorithm leads to a significant reduction in CPU time and storage requirements as compared with the conventional FDTD. The simulation results are in good agreement with the results obtained by other methods and measurements     

高速数字电路PCB中串扰问题的研究与仿真

针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

Improved global rational approximation macromodeling algorithm fornetworks characterized by frequency-sampled data

Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution     

平行传输线间串扰的仿真及分析

在高速电路设计中,信号完整性问题越来越突出,已经成为高速电路设计师不可避免的问题。该文重点研究了平行传输线间的串扰问题,通过信号完整性分析软件Hyperlynx建立了三线串扰模型并进行仿真分析,最后提出高速PCB设计中减小串扰噪声的策略。     

Electromagnetic analysis of multiconductor losses and dispersion in high-speed interconnects

A self-consistent electromagnetic analysis of multiconductor transmission lines is presented for high-speed, high-density MMIC's and VLSI interconnects. In contrast to classical approach, this analysis handles the multiconductor as normal dielectric with high conductivity in electromagnetic simulation. Therefore, dispersion and loss effects can exactly be described in this model. Examples of interconnect circuits with up to four conductors are analyzed for dispersion and frequency-dependent losses. Propagation characteristics of multimode along symmetrical and asymmetrical multiconductor are obtained. Some inherent influences of losses on high-density interconnects and physical dependence of these effects are also discussed.     

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-μm technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator     

Optimization of Driver Preemphasis for On-Chip Interconnects

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of the interconnect output signal, the corresponding input signals can be derived analytically. The result can be used to guide and optimize the design of interconnect preemphasis drivers. Numerical examples are shown for both lossy RC and RLC distributed lines. Analysis shows that optimized driving voltage and current can increase the interconnect bandwidth without voltage overshoot at the output. The significance of an interconnect inductance is also evaluated with this technique.     

Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels

With the ever increasing signal speeds, signal integrity issues of high-speed VLSI designs are presenting increasingly difficult challenges for state-of-the-art modeling and simulation tools. Consequently, characterization and passive macromodeling of high-speed modules such as interconnects, vias, and packages based on tabulated data are becoming important. This paper presents a fast algorithm for passivity verification and enforcement of large order macromodels of scattering parameter based multiport subnetworks. Numerous examples tested on this algorithm demonstrate a significant speed-up compared to the existing algorithms in the literature     

Modeling DC power-bus structures with vertical discontinuitiesusing a circuit extraction approach based on a mixed-potential integralequation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design     

Design and Characterization of the EBG Waveguide-Based Interconnects

An alternative signal guiding structure, which can be integrated within the printed circuit substrates, is investigated in this paper. The structure is realized by forming a rectangular waveguide in a 2-D electromagnetic bandgap (EBG) substrate. In this manner, a bandpass interconnect is provided that proves to be a promising technology for the high-speed/high-frequency system design. A systematic approach to the design and optimization of this interconnect is presented here followed by investigation of various bend geometries. The studied structures exhibit very low levels of loss and leakage when inspected at tens of gigahertz frequency range. Moreover, the near-end and the far-end crosstalks are monitored in multiple interconnects proving the high efficiency of this alternative routing structure in dense layouts. Nonetheless, the crosstalk performance is degraded as the coplanar microstrip-to-waveguide transitions are added. These transitions are essentially tapered microstrip lines that are connected to other circuitries. Continuous via fences are inserted in the transition sections of multiple structures demonstrating significant improvement in the crosstalk performance.     

高速数字通信中的远端串扰建模分析

当今电子产品不断更新换代,性能不断提升,需要处理的数据量不断增大,信号的速度也随之越来越快,印刷电路板（PCB）的面积反而越来越小。这就导致信号线的密度越来越大,不同信号线之间信号就会出现相互影响,也就是串扰。针对高速数字通信系统中传输链路之间的信号间串扰,建立等效电路模型,推导出远端串扰噪音的计算公式,提出改善措施,并最终使用HSPICE进行了仿真验证。     

Isolation effects in single- and dual-plane VLSI interconnects

The issue of interline coupling in high-speed VLSI interconnects is addressed. A full-wave-based technique is used to numerically solve for the modes and hence the line voltages and currents for multiconductor microstrip. The accuracy of these results is compared with time-domain experimental data. Isolation lines placed between signal lines and grounded at both ends are considered as a means of significantly reducing crosstalk. It is shown that the performance of such lines depends on several factors such as relative mode velocities, signal rise and fall times, and line length. These points are illuminated by considering the effects of isolation lines in two geometries of interest in high-speed integrated circuits. On the basis of these results one can determine the usefulness of isolation lines for a given geometry