Sheet resistance variations of phosphorus implanted silicon at elevated temperatures

Silicon has been implanted to high doses (2 × 10¹⁵–2 × 10¹⁶ ions cm^?2) with 40 keVP⁺ at constant temperatures in the range 20–300°C. The sheet resistance following implantation is shown to have a break point at 167°C in its temperature variation characteristic. It is suggested that sheet resistance variations result from changes in the depth of the amorphous layer formed during implantation. A dose rate effect has also been observed. The behaviour correlates with the variations which have been observed on colour-banded wafers. It is also demonstrated that small temperature rises during implantation can result in significant variations in the sheet resistance, even after high temperature annealing.     

The effect of argon implantation on the conductivity of boron implanted silicon

Silicon wafers have been implanted with boron (3 × 10¹⁴ or 1 × 10¹⁵ ions cm^?2) and with argon (up to 1 × 10¹⁵ ions cm^?2). The energies were chosen to approximately superimpose the two impurity distributions. After the boron and argon implantations the sheet resistance of each wafer was measured following annealing in nitrogen at temperatures in the range 400–1050°C. The highest dose argon implantation produced an increase in sheet resistance which persisted throughout the entire temperature range. Lower argon doses produced a reduction in sheet resistance for anneal temperatures between 550 and 800°C. The magnitude of the reduction is a function of the boron and argon doses and of the anneal temperatures. The greatest reduction, observed after a 600°C anneal, was by a factor of 5.8. Above 800°C the low dose argon did not affect the sheet resistance.The observed reduction in sheet resistance is expected to lead to an improvement in metal to p-type silicon contacts. A particular application is in the contacts to resistors in fast bipolar logic circuits. As high electrical activity can be obtained at moderate annealing temperatures with combined boron and argon implantations, these implantations can be carried out at a late stage in an integrated circuit process schedule without the danger of additional movement of existing junctions.     

Current transport in fluorine implanted GaAs

Effects of fluorine implantation in GaAs have been investigated by electrical characterization. Ion implantation at 100 keV energy was conducted with doses of 10¹¹ and 10¹²/cm². The effect of fluorine implantation on current-voltage (I-V) characteristics of Schottky diodes was significant. Carrier compensation was observed after implantation by the improved I-V characteristics. The lower dose implanted samples showed thermionic emission dominated characteristics in the measurement temperature range of 300 to 100K. The starting wafer and the low dose implanted samples after rapid thermal annealing (RTA) showed similar I-V properties with excess current in the lower temperature range dominated by recombination. The higher dose implanted samples showed increased excess current in the whole temperature range which may result from the severe damage-induced surface recombination. These samples after RTA treatment did not recover from implantation damage as in the low dose implantation case. However, very good I-V characteristics were seen in the higher dose implanted samples after RTA. The influence of the higher dose ion implantation was to produce more thermal stability. The results show the potential application of fluorine implantation in GaAs device fabrication.     

Rapid thermal annealing of si implanted gaas

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 10¹² to 1 × 10¹⁴/cm². The wafers were encapsulated with Si₃N₄ and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 10¹²/cm² at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 10¹³ an activation energy of 1.7 eV was obtained. For a dose of 4 × 10¹² at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm²/V-s. Mobilities decrease to 4000 at a dose of 1 × 10¹³ and to 2500 cm²/V-s at 1 × 10¹⁴/cm². At doses above 1 × 10¹³ the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.     

Rapid Thermal annealing of si implanted GaAs

Rapid thermal annealing (RTA) with incoherent light from tungsten lamps shows high potential relative to the conventional furnace annealing (FA) to activate the implanted dopant. Due to the short time annealing, it could completely eliminate the re-diffusion of dopant and host atom. For the Si implantation with dose of 2 × 10¹⁴ cm², the electrical activity of 78% for RTA was higher than that of the FA. But for this short time, some defects measured by deep level transient spectroscopy (DLTS) were hard to remove. A two-step annealing was suggested by the combination of high temperature RTA (1000° C) and FA (700° C). After the post-FA, the defects would be removed to a great extent, and the electrical activity of dopant also increased. With the dose of 2 x 1013 cm^-2, the activity attained after the two step annealing was 92.5%, which may be the highest value according to our knowledge for rapid thermal annealing on Si ion implanted GaAs.     

Hot-implantation of nitrogen donors into p- type α-SiC and characterization of n+-p junction

N⁺ implantation into p-type a-SiC (6H-SiC, 4H-SiC) epilayers at elevated temperatures was investigated and compared with implantation at room temperature (RT). When the implant dose exceeded 4 × 10₁₅ cm₋₂, a complete amorphous layer was formed in RT implantation and severe damage remained even after post implantation annealing at 1500°C. By employing hot implantation at 500~800°C, the formation of a complete amorphous layer was suppressed and the residual damage after annealing was significantly reduced. For implant doses higher than 10¹⁵ cm⁻², the sheet resistance of implanted layers was much reduced by hot implantation. The lowest sheet resistance of 542Ω/ was obtained by implantation at 500 ~ 800°C with a 4 × 10¹⁵ cm⁻² dose. Characterization of n⁺-p junctions fabricated by N⁺ implantation into p-type epilayers was carried out in detail. The net doping concentration in the region close to the junction showed a linearly graded profile. The forward current was clearly divided into two components of diffusion and recombination. A high breakdown voltage of 615 ∼ 810V, that is almost an ideal value, was obtained, even if the implant dose exceeded 10¹⁵ cm⁻². By employing hot implantation at 800°C, the reverse leakage current was significantly reduced.     

Characterization of phosphorus implantation in 4H-SiC

We report the characterization of phosphorus implantation in 4H-SiC. The implanted layers are characterized by analytical techniques (secondary ion mass spectrometry, transmission electron microscopy) as well as electrical and a sheet resistance value as low as 160 Ω/□ has been measured. We have also studied the effect of annealing time and temperature on activation of phosphorus implants. It has been shown to possible to obtain low sheet resistance (∼260 Ω/□) by annealing at a temperature as low as 1200°C. High-dose (∼ 4 × 10¹⁵ cm⁻²) implants are found to have a higher sheet resistance than that on lower dose implants which is attributed to the near-surface depletion of the dopant during high temperature anneal. Different implantation dosages were utilized for the experiments and subsequently junction rectifiers were fabricated. Forward characteristics of these diodes are observed to obey a generalized Sah-Noyce-Shockly multiple level recombination model with four shallow levels and one deep level.     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.     

Rapid thermal annealing of dual Si and P implants in InP

In this study we evaluate the effects of dual implantation with different doses of Si and P on dopant activation efficiency and carrier mobility in InP:Fe. The implants were activated by a rapid thermal annealing step carried out in an optimized phosphoruscontaining ambient. For high dose implants (10¹⁴–10¹⁵ cm⁻²), which are typically employed for source/drain regions in FETs, dual implantation of equal doses of Si and P results in a higher sheet carrier concentration and lower sheet resistance. For 10¹⁴ cm⁻² Si implants at 150 keV, the optimal P co-implant dose is equal to the Si dose for most anneal temperatures. We obtain an activation efficiency of ∼70% for dual implanted samples annealed at 850° C for 10 sec. The high activation efficiencies and low sheet resistances obtained in this study emphasize the importance of stoichiometry control through the use of P co-implants and a phosphorus-containing ambient during the thermal processing of InP.     

Aluminum and boron ion implantations into 6H-SiC epilayers

Aluminum and boron ion implantations into n-type 6H-SiC epilayers have been systematically investigated. Redistribution of implanted atoms during high-temperature annealing at 1500°C is negligibly small. The critical implant dose for amorphization is estimated to be 1 × 10¹⁵ cm⁻² for Al⁺ implantation and 5 × 10¹⁵ cm^-2 for B⁺ implantation. By Al⁺ implantation followed with 1500°C-annealing, p-type layers with a sheet resistance of 22 kΩ/^— can be obtained. B⁺ implantation results in the formation of highly resistive layers, which may be attributed to the deep B acceptor level.     

Some annealing properties of low-energy-antimony—implanted silicon resistors

Shallow-implanted antimony in silicon can be used in fabricating n-type silicon resistors with very low temperature coefficient of resistance (TCR), controllably and reproducibly. This paper reports a study of the sheet resistance of silicon resistors implanted with ¹²¹Sb at 10 keV, for various doses and annealing conditions. The methods used in fabricating samples and taking measurements were described in an earlier paper[1]. For high doses, ～ 10¹⁵ Sb/cm², we found that two-stage annealing[2]—preannealing at 550°C followed by annealing at 1000°C—improves the electrical conductivity. For low doses, ～10¹² Sb/cm², the final annealing determines the conductivity. For medium doses, ～10¹³–10¹⁴ Sb/cm², the interplay of damage-annealing and activation of Sb in Si introduces complications, giving a crossover of shet resistance vs implant dose for various annealing temperatures. For doses around 3 × 10¹³ cm^?2, the resistances are very insensitive to the details of annealing sequence and temperature; also the TCR is very low, about 50 ppm/°C. The effect of annealing conditions for various doses, resistivities and TCR values are discussed.     

Phosphorus implantation into 4H-silicon carbide

Sheet resistances in nitrogen- and phosphorus-implanted 4H-SiC are measured to assess the time and temperature dependencies of this variable. In 4H-SiC implanted with 3 × 10¹⁵ cm^?2 nitrogen ions to a depth of 2800 Å, the minimum sheet resistance observed is 534 Ω/□. The minimum sheet resistance in 4H-SiC implanted with 4 × 10¹⁵ cm^?2 phosphorus ions to a depth of 4000 Å is 51 Ω/□, a record low value for any implanted element into any polytype of SiC. Time-independent sheet resistances are observed following anneals at 1700°C for nitrogen and phosphorus samples. Lower temperature anneals produce sheet resistances which decrease monotonically with increasing time of anneal. Overall, sheet resistances from phosphorus-implanted 4H-SiC are an order of magnitude below those measured from nitrogen implanted samples. The response of phosphorus to low-temperature annealing is significant, and sheet resistances below 500 Ω/□ are achieved at 1200°C. Activation of phosphorus is attempted in an oxidizing atmosphere with and without prior argon annealing. A three-hour gate oxidation in wet O₂ at 1150°C, followed by a 30 min argon anneal, produced a sheet resistance of 1081 Ω/□. Oxidation after argon annealing caused sheet resistances to increase by about 20% compared to samples subjected solely to argon annealing. It is also found that oxide growth rates are much higher over phosphorus implanted than over unimplanted 4H-SiC. Reasons for the disparity in sheet resistances between nitrogen and phosphorus implants, and for the difference in oxide growth rates are suggested.     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Photothermal Activation of Shallow Dopants Implanted in Silicon

Dopant impurities were implanted at high dose and low energy (10¹⁵ cm⁻², 0.5–2.2 keV) into double-side polished 200 mm diameter silicon wafers and electrically activated to form p–n junctions by 10 s anneals at temperatures of 1,025, 1,050, and 1,075°C by optical heating with tungsten incandescent lamps. Activation was studied for P, As, B, and BF₂ species implanted on one wafer side and for P and BF₂ implanted on both sides of the wafer. Measurements included electrical sheet resistance (Rs) and oxide film thickness. A heavily boron-doped wafer, which is optically opaque, was used as a hot shield to prevent direct exposure to lamp radiation on the adjacent side of the test wafer. Two wafers with opposing orientations with respect to the shield wafer were annealed for comparison of exposure to, or shielding from, direct lamp illumination. Differences in sheet resistance for the two wafer orientations ranged from 4% to 60%. n-Type dopants implanted in p-type wafers yielded higher Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been reduced. p-Type dopants implanted in n-type wafers yielded lower Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been increased. Effective temperature differences larger than 5°C, which were observed for the P, B, and BF₂ implants, exceeded experimental uncertainty in temperature control.     

Selenium implantation in GaAs

The dependence of carrier concentration and mobility profiles on the dose of 400 keV Se ions implanted into Cr-doped semi-insulating GaAs, and on the annealing temperature has been studied for doses ranging from 3 × 10¹²/cm² to 2 × 10¹⁵/cm² and for annealing temperatures between 800 and 1000°C. Sputtered aluminum oxy-nitride and silicon nitride films were used as encapsulants for protection of the implanted surface during annealing treatments. The carrier profiles exhibited deep tails for implantations along both random and {110} planar directions. It was found that annealing temperatures of 900°C or above were necessary to obtain high carrier density and mobility values for implantation doses above 1 × 10¹⁴/cm². Samples encapsulated with aluminum oxy-nitride films exhibited 3 to 4 times higher carrier concentration values and also slightly higher mobility values than those encapsulated with silicon nitride films. The maximum carrier concentration obtained was about 4 × 10¹⁸/cm³ with aluminum oxy-nitride films as the encapsulant.     

The role of outdiffusion in the activation of high dose Mg implantations in InP

We have studied the annealing behaviour of magnesium implanted in indium phosphide. The activated fraction of dopants was found to depend strongly on implanted dose and substrate temperature during implantation. Low activation for high dose (10¹⁵ cm⁻²) implantations was found to be a result of pronounced outdiffusion (80%). We also found a large variation in the apparent activation energy for implantation temperatures between room temperature and 300° C.     

High-Dose Phosphorus-Implanted 4H-SiC: Microwave and Conventional Post-Implantation Annealing at Temperatures ≥1700°C

Semi-insulating 4H-SiC ⟨0001⟩ wafers have been phosphorus ion implanted at 500°C to obtain phosphorus box depth profiles with dopant concentration from 5 × 10¹⁹ cm⁻³ to 8 × 10²⁰ cm⁻³. These samples have been annealed by microwave and conventional inductively heated systems in the temperature range 1700°C to 2050°C. Resistivity, Hall electron density, and Hall mobility of the phosphorus-implanted and annealed 4H-SiC layers have been measured in the temperature range from room temperature to 450°C. The high-resolution x-ray diffraction and rocking curve of both virgin and processed 4H-SiC samples have been analyzed to obtain the sample crystal quality up to about 3 μm depth from the wafer surface. For both increasing implanted phosphorus concentration and increasing post-implantation annealing temperature the implanted material resistivity decreases to an asymptotic value of about 1.5 × 10⁻³ Ω cm. Increasing the implanted phosphorus concentration and post-implantation annealing temperature beyond 4 × 10²⁰ cm⁻³ and 2000°C, respectively, does not bring any apparent benefit with respect to the minimum obtainable resistivity. Sheet resistance and sheet electron density increase with increasing measurement temperature. Electron density saturates at 1.5 × 10²⁰ cm⁻³ for implanted phosphorus plateau values ≥4 × 10²⁰ cm⁻³, irrespective of the post-implantation annealing method. Implantation produces an increase of the lattice parameter in the bulk 4H-SiC underneath the phosphorus-implanted layer. Microwave and conventional annealing produce a further increase of the lattice parameter in such a depth region and an equivalent recovered lattice in the phosphorus-implanted layers.     

The effects of incomplete annealing on the temperature dependence of sheet resistance and gage factor in aluminum and phosphorus implanted silicon on sapphire

The temperature coefficient of resistivity (TCR) of ion implanted silicon can be significantly reduced by partially annealing the crystal damage produced during implantation. The extent to which this method can be used to temperature compensate the resistivity and the gage factor has been determined for 300 ohm-cm silicon on sapphire implanted with either 100 keV Al²⁷ or P³¹ ions. The implantations were made at room temperature parallel to the 〈100〉 axis and in four fluences ranging from 1 × 10¹³cm^?2 to 1·25 × 10¹⁵ cm^?2. Sheet resistance, Hall coefficient, and effective mobility were measured from ?150°C to 150°C for various anneal temperatures. It was possible to obtain very low temperature dependences of sheet resistance at 300°K for all dopant fluences by appropriate partial annealing. On samples having the lowest temperature dependence of sheet resistance, the gage factor was measured from ?75°C to 75°C. The measurements were made along the 〈100〉 direction for phosphorus doped samples, and along the 〈110〉 direction for aluminum doped samples for all four fluences. The gage factor and its temperature dependence for these crystal orientations are not drastically affected by the crystal damage. These results are interpreted in terms of a model previously developed to explain the effect of electron damage on the temperature dependence of the resistivity and the piezoresistance of silicon.     

Activation efficiencies for a standard qualification implant in gaas annealed by a rapid thermal process

Recently a 150 keV, 2 × 10¹² cm⁻², Si²⁹ implant, with furnace annealing at 850° C for 10 min with a GaAs proximity wafer, has been proposed as a standard qualification test for semi-insulating GaAs. In general, the electrical activation efficiency of implanted wafers is determined either from Hall effect data or from capacitance-voltage (C-V) data; however, the Hall effect method requires sizable depletion corrections at low implant doses. In this paper, we examine the proposed standard, and the methods of determining activation, from three points of view: (1) rapid-thermal annealing (RTA) vs furnace annealing; (2) a Si proximity cap vs a GaAs proximity cap; and (3) Hall effect vs C-V. Our conclusions are: (1) RTA produces higher activation efficiencies, at least for our particular wafers, than furnace annealing; (2) Si and GaAs proximity caps produce nearly equivalent activation efficiencies; and (3) the Hall effect, when corrected for depletion, is a useful technique for measuring activation efficiency, and appears to be more accurate than the C-V technique.     

Internal-getter formation in nitrogen-doped dislocation-free silicon wafers

An experimental study is reported concerning the formation of defects in nitrogen-doped dislocation-free silicon wafers under a multistage heat treatment to produce an internal getter, the first stage being rapid thermal annealing (RTA) under different conditions. The experiments are conducted on p-Si(100) wafers of diameter 200 mm with an oxygen content of (6−7) × 10¹⁷ cm⁻³ and a doping level of 1.6 × 10¹⁴ cm⁻³, the resistivity being 10–12 ω cm. The processed wafers are examined by optical microscopy and transmission electron microscopy. With normal conditions of RTA (argon, 1250°C, 20 s), the process is found to be incapable of creating a defect-free subsurface layer of adequate thickness, though it is able to provide the desired system of defects in the bulk. The aim is achieved by changing to sequential RTA in oxygen and argon as the first stage. The reasons for the results are presented.