带电平位移电路的H桥高端功率管栅极驱动电路

提出了一种带高压电平位移电路的H桥高端功率管栅极驱动电路.电平位移电路采用脉冲下拉方式实现高压电平位移,与一般的方波下拉方式相比,有效地减小了电路的功耗.分析了脉冲下拉方式电平位移电路的工作原理与实现方式,以此为基础,设计了H桥高端驱动电路.基于5μm高压BCD工艺,采用Spectres进行电路仿真,完成了电路版图设计和流片测试.结果显示,设计的高端驱动电路能很好地实现高端功率管栅极电位的悬浮抬升.     

IGCT门极驱动特性研究

IGCT（集成门极换流晶闸管）是一种同时结合GTO和IGBT优点的新型大功率半导体开关器件。本文首先结合4500V／4000A IGBT驱动电路设计，分忻IGCT基本工作原理和驱动电路工作原理。最后通过低压大电流实验，验证丁IGCT开通、关断原理。证明了IGCT在相同环境温度的导通状态下，门极驱动电流对导通睚降没有影响。     

一种高速、高共模噪声抗扰的电平位移电路

介绍了一种应用于GaN驱动的0.35μm HV CMOS工艺的高速、高共模噪声抗扰的电平位移电路。该电路采用高速电流镜和双锁存结构,并增加共模抗扰辅助电路,大大提高了传输速度和对共模噪声的抗扰能力。该高速、高共模噪声抗扰的电平位移电路主要用于驱动增强型GaN的高压半桥栅驱动。仿真结果显示该电平位移电路上升沿传输延时1.03 ns,下降沿传输延时1.15 ns,可承受GaN高压半桥栅驱动开关节点SW处电压浮动50 V/ns。     

适用于GaN栅极驱动的自适应死区时间控制电路

设计了一种适用于GaN栅极驱动的自适应死区时间控制电路,该电路具有低延时、低功耗、高速、高开关频率的特点。电路通过单脉冲产生电路检测开关节点电压,以实现零静态功耗;加入互锁电路以防误触发,消除了由开关节点毛刺导致的上下管直通的现象。电路基于SMIC 0.18μm BCD工艺设计,仿真结果表明,死区时间可随负载变化而自适应调整,且当最坏情况开关节点电压的dv/dt=48 V/ns时,电路高低侧死区时间误差仅为1.59 ns和2.69 ns。     

在SMPS应用中选择IGBT和MOSFET的比较

开关电源（Switch Mode Power Supply;SMPS）的性能在很大程度上依赖于功率半导体器件的选择,即开关管和整流器。虽然没有万全的方案来解决选择IGBT还是MOSFET的问题,但针对特定SMPS应用中的IGBT和MOSFET进行性能比较,确定关键参数的范围还是能起到一定的参考作用。本文将对一些参数进行探讨,     

1200 V功率MOS栅驱动集成电路的设计

文章在国内首次设计并研制出1200V功率MOS栅驱劝集成电路。该电路最高偏置电压(Voffset(max))为1200V，最大输出峰值电流为1A，最高工作频率100kHz，温度范围-55～125℃，可同时驱劝系统中用于三相图腾柱式输出的高低端功率器件，是SPIC的一种典型电路。     

基于峰值电流模控制的浮动栅驱动电路

设计了一种基于峰值电流模控制的浮动栅驱动电路,包括浮动栅宽电路和浮动栅压电路。电感电流的峰值由误差放大器的输出电压决定,不需要额外的负载电流信息进行浮动栅控制。可以根据负载电流的大小自适应调节功率管的栅宽和栅压,使效率得到优化。仿真结果表明,在1 MHz开关频率、5 V输入、0.8 V输出的双N管Buck变换器中,采用浮动栅驱动控制的Buck变换器与普通的Buck变换器相比,在轻载情况下最多可达到10%的效率提升。     

一种低成本高精度温度测量电路

给出用晶体管3DG6作为温度传感器,电压/频率转换器和单片机组成的温度测量仪的具体方案及其调校简便和自动补偿的实现方法。     

MOSFET栅极驱动的优化设计

介绍了MOS管的电路模型、开关过程、输入输出电容、等效电容、电荷存储，及其对MOS管驱动波形的影响和驱动波形的优化设计实例。     

"单正向"栅驱动IGBT简化驱动电路

目前,为了防止高dV/dt应用于桥式电路中的IGBT时产生瞬时集电极电流,设计人员一般会设计栅特性是需要负偏置栅驱动的IGBT.然而提供负偏置增加了电路的复杂性,也很难使用高压集成电路(HVIC)栅驱动器,因为这些IC是专为接地操作而设计--与控制电路相同.     

基于有源电力滤波器的IGBT驱动及保护研究

介绍了采用M57962L设计的有源滤波器中绝缘栅场效应晶体管（IGBT）驱动器的驱动原理和电路特点,对IG—BT的栅极驱动特性、栅极串联电阻进行了探讨,给出过流保护和过压吸收的有效方法。样机试验证明了此种设计方案可靠、有效。     

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.     

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

高k栅介质纳米MOSFET栅电流模型

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

A concise study of neutron irradiation effects on power MOSFETs and IGBTs

Over the past years there have been growing concerns on the adverse effects of atmospheric neutrons on power semiconductors even at sea level. In this paper we report recent results of neutron irradiation (1.9 MeV) experiments conducted on 650 V Super-Junction MOSFETs and Field-Stop Trench Insulated Gate Bipolar Transistors (IGBTs). The typical experiments found in literature which study the irradiation of power electronics chose a white line spectrum of neutron energies, ranging from 1 to 180 MeV; however, we have deliberately chosen to study the effect of monochromatic radiation of fast neutrons, as a first in a series of experiments, to better understand the full range of interactions from fast to ultra fast neutrons (100 MeV). We show that a multitude of failure modes already appear at neutron energies of 1.9 MeV ranging from gate oxide degradation to single event effects (SEE). Moreover an outstanding ruggedness of devices is demonstrated, which shows no failures at 80% rated break down and below under extreme aging conditions.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.     

纳米级MOSFET隧穿栅电流量子模型

运用一种全量子模型,研究高k栅介质纳米MOSFET(场效应管)栅电流,特别适用于各种材料高k栅介质和高k叠栅介质纳米MOSFET。使用该方法,研究了高k栅介质中氮含量等元素对栅极电流的影响,并对模拟结果进行了分析比较。结果显示,为了最大限度减少MOS器件的栅泄漏电流,需要优化介质中的氮含量。通过对比表明,模型与实验结果符合。     

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation represents an upper limit of what is possible from any type of model, but that good parameter extraction is required to most closely approach that limit. The individual model types presently in common use are examined, with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of circuits, and criteria that a circuit design consumer can employ to judge a model before using it for circuit design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of MOSFET modeling for circuit simulation are considered.     

功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.