Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N_s=N_s(VG) characteristics of the device toward lower gate voltages     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

Efficient Monte Carlo device modeling

A single-particle approach to full-band Monte Carlo device simulation is presented which allows an efficient computation of drain, substrate and gate currents in deep submicron MOSFETs. In this approach, phase-space elements are visited according to the distribution of real electrons. This scheme is well adapted to a test-function evaluation of the drain current, which emphasizes regions with large drift velocities (i.e., in the inversion channel), a substrate current evaluation via the impact ionization generation rate (i.e., in the LDD region with relatively high electron temperature and density) and a computation of the gate current in the dominant direct-tunneling regime caused by relatively cold electrons (i.e., directly under the gate at the source well of the inversion channel). Other important features are an efficient treatment of impurity scattering, a phase-space steplike propagation of the electron allowing to minimize self-scattering, just-before-scattering gathering of statistics, and the use of a frozen electric field obtained from a drift-diffusion simulation. As an example an 0.1-μm n-MOSFET is simulated where typically 30 minutes of CPU time are necessary per bias point for practically sufficient accuracy     

Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling

Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.     

纳电子器件的少电子输运性质及应用

在介绍纳电子器件基本输运理论基础上,着重分析量子点结构器件模型,讨论了量子点上能级分立和电子填充的各种情况,以及电子自旋的影响,特别强调了纳米限制系统中局域态电子和非局域态电子相互作用特征。综述了目前纳电子器件的研究进展及其应用。     

Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.     

Quantum effects of electrons and holes in the MOSFET inversion layer

Based on the study of mobility degradation due to the gate field, two different mechanisms of the quantum effects are proposed for inversion carriers: i) the quantization of inversion carriers and the populating of the upper sub-bands, which tend to increase the dependence of mobility on the gate field; and ii) the quantum mechanical channel broadening, which tends to decrease the dependence of mobility on the gate field. Experimental data for electrons and holes at 25 and 125°C will be reported and analyzed.     

The bloch-FET—A lateral surface superlattice device

We describe a lateral surface superlattice device embedded in a MOSFET structure. Control of the inversion layer density and the two-dimensional quantized inversion layer itself allows optimizing the sub-band energy level spacing for a variety of applications. In particular, the narrow bands that arise in the inversion layer itself lead to the possibility of readily achieving negative differential conductivity in the transport properties of electrons through the device.     

Low-temperature characterization of buried-channel NMOST

A comprehensive characterization of buried-channel NMOS transistors at low temperatures down to 30 K is reported. The mobilities of both surface (accumulation) and bulk (buried-channel) electrons were determined as a function of surface electric field and gate bias voltage, respectively, at low temperatures. Both surface electron mobility and buried-channel electron mobility increase with decreasing temperatures. However, a peak in the buried-channel electron mobility is observed around 80 K if the neutral region extends to regions of high impurity concentrations near the surface. A modified MOSCAP (Poisson solver) was used to obtain spatial distributions of carriers and to predict the C-V curves. Low-frequency noise measurements at low temperatures were carried out at gate voltages corresponding to the accumulation, depletion, and inversion modes of operation of the device. In the accumulation mode, a 1/f dependence is observed similar to surface-channel devices. In the depletion mode, a generation-recombination type of noise is observed with a peak around 150 K. In the inversion mode, noise that is related to the hole inversion layer is observed     

An In0.53Ga0.47As p-channel MOSFET with plasma-grown native oxide insulated gate

We describe the operation of an In0.53Ga0.47As p-channel inversion mode MOSFET with plasma grown native oxide insulated gate. This device exhibits a transconductance of 4 mS/mm and an effective channel mobility of more than 50% of the bulk hole mobility. This device is the first demonstration of a native oxide insulated gate MOSFET in the In1-xGaxAsyP1-ymaterial system.     

Simulation of a long term memory device with a full bandstructureMonte Carlo approach

Simulations of charging characteristics of a long term memory device, based on a floating gate structure, are presented. The analysis requires the inclusion of hot electron effects and a detailed account of the semiconductor bandstructure, because device operation is based on the injection of electrons into the gate oxide high above the silicon conduction band edge. We have developed a Monte Carlo simulator based on a full bandstructure approach which accurately accounts for the high energy tail of the electron distribution function. For practical simulation of the prototype structure; with 3.0-μm source-drain separation, the simulator is used as a post-processor on the potential profile obtained from a PISCES IIB drift-diffusion solution. The computations are in quantitative agreement with experimental results for the gate injection current, measured at fixed drain and gate biases     

减少纳米MOS器件栅电流的研究分析

采用Schroedinger-Poisson方程自洽全量子求解法研究了MOS器件不同介质材料和栅结构栅电流,该模型对栅电流中的三维电流成分用行波统一地计算;对二维栅电流成分通过反型层势阱中准束缚态的隧穿率计算。模拟得出栅极电流与实验结果符合。研究结果表明,采用高愚栅介质材料、p-MOSFET或双栅结构对栅电流的减少有明显的作用,这一结果可望对器件性能作出预计并对其研制提供指导。     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.     

A comparison of wave-function penetration effects on gatecapacitance in deep submicron n- and p-MOSFETs

We have calculated the effects of wave function penetration into the gate-oxide on the modeling of gate capacitance in deep submicron p-MOSFETs on (100) silicon for the first time. These results are compared to those of n-MOSFETs. Self-consistent calculations show that contrary to the common belief, penetration effects are more pronounced in p-MOS devices. The error in inversion capacitance due to neglect of penetration effects has opposite dependence on substrate doping density for n-MOS and p-MOS structures. Consequently, the error in gate capacitance for an n-MOSFET in strong inversion is strongly dependent on doping density, while that for a p-MOSFET essentially does not depend on doping density. An explanation for this unusual result is also provided. Although the error in gate capacitance is only a few percent, it will have nontrivial effects on device parameter extraction from capacitance-voltage (C-V) measurements     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

3-D computer simulation of single-electron charging in siliconnanocrystal floating gate flash memory devices

The operation of a silicon nanocrystal quantum-dot based flash memory device is simulated numerically with emphasis on energy and charge quantization in the quantum-dot. The simulation involves the self-consistent solution of three-dimensional (3-D) Poisson and Schrodinger-like equations, with the Slater rule for determining the charging voltage. We also compute the capacitance-voltage characteristics of the device and derive the threshold voltage, V_T , variation with single-electron charging as a function of design parameters     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

基于DMD的外腔量子点激光器性能研究

为了取得更加完善的外腔量子点激光器(QDL)测试 数据,构建了基于数字微镜器件(DMD,digital micro-mirror device)的InAs/InP量子 点外腔QDL。测量了其 光谱特性以及调谐范围,得到了基于DMD的外腔QDL调谐范围和相应的模式变 化。在理论和实验上与基于光栅的外腔QDL性能进行了比较,得到了在角色 散和反射光谱中与光栅的区别,实现了将DMD应用于外腔QDL中而获得的一种 新方法。     

Experimental Investigation on the Quasi-Ballistic Transport: Part II—Backscattering Coefficient Extraction and Link With the Mobility

Using a new extraction methodology taking into account multisubband population and carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic ratios, and injection velocities of n- and p-FDSOI devices with gate lengths down to 30 nm in the saturated and, for the first time, in the linear regimes. The evolution of these quasi-ballistic parameters is examined as a function of the inversion charge in the channel and at temperatures ranging from 50 to 293 K, showing stronger ballistic ratios in the saturated regime than in the linear one. We particularly focus on the linear regime, and a model linking ballisticity ratios and effective mobility is proposed and validated experimentally for different gate lengths. According to the experimental evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature, we investigate the mobility degradation with decreasing gate lengths, highlighting the importance of Coulomb scattering on this unexpected mobility behavior.      

Alpha-particle-induced collected charge model in SOI-DRAM's

We have developed a model for collected charges induced by an alpha-particle for SOI-DRAMs which assumes that the body capacitance equals the gate capacitance and that holes do not recombine with electrons. The validity of our model was supported by three-dimensional (3-D) device simulations that considered various gate lengths, gate oxide thicknesses, and flat-band voltages. The work function difference between the gate and body materials caused a significant increase in the current gain. The vertical band of the body region should therefore be flat to suppress the collected charge. A thinner gate oxide would also suppress the collected charge during a refresh interval. This finding could not be obtained from the conventional equation