Graphene-like metal-on-silicon field-effect transistor

This paper presents a field-effect transistor with a channel consisting of a two-dimensional electron gas located at the interface between an ultrathin metallic film of Ni and a p-type Si(111) substrate. The gate length is L = 2 μm, its width is W = 180 μm, and the source-drain separation is 188 μm, the role of the gate dielectric being played by the surface states of the ultrathin metal layer. We have demonstrated that the two-dimensional electron gas channel is modulated by the gate voltage. The dependence of the drain current on the drain voltage has no saturation region, similar to a field-effect transistor based on graphene. The drain current is 2 mA at a drain voltage of 3 V and a gate voltage of 1.07 V, while the transconductance is 0.6 mS for a drain voltage of 6 V and a gate voltage of 1 V. However, the transport in this transistor is not ambipolar, as in graphene, but unipolar.     

InAs1-xPx nanowires for device engineering

We present the growth of homogeneous InAs(1-x)P(x) nanowires as well as InAs(1-x)P(x) heterostructure segments in InAs nanowires with P concentrations varying from 22% to 100%. The incorporation of P has been studied as a function of TBP/TBAs ratio, temperature, and diameter of the wires. The crystal structure of the InAs as well as the InAs(1-x)P(x) segments were found to be wurtzite as determined from high-resolution transmission electron microscopy. Furthermore, temperature-dependent electrical transport measurements were performed on individual heterostructured wires to extract the conduction band offset of InAs(1-x)P(x) relative to InAs as a function of composition. From these measurements we extract a value of the linear coefficient of the conduction band versus x of 0.6 eV and a nonlinear coefficient, or bowing parameter, of 0.2 eV. Finally, homogeneous InAs(0.8)P(0.2) nanowires were shown to have a nondegenerate n-type doping and function as field-effect transistors at room temperature.     

Organic field-effect transistors containing a SiO2 nanoparticle thin film as the gate dielectric

In this article, we report the fabrication of organic field-effect transistors using self-assembled SiO2 as a gate dielectric material and pentacene as a semiconductor. The dielectric layer was self-assembled with 10 layers of SiO2 nanoparticles 45 nm in diameter, and its breakdown field was larger than 0.57 MV/cm. Being a low-cost and low-temperature process, the layer-by-layer self-assembly is particularly suitable for organic field-effect transistor fabrication. The pentacene was thermally evaporated on the substrate under high vacuum at the room temperature. The fabricated transistor has a threshold voltage of 0.3 V, field-effect mobility of 0.05 cm2/Vs, and slope of 1.4 V/decade.     

Synthesis and characterization of anthracene derivative for organic field-effect transistor fabrication

Here we report on the synthesis and characterization of anthracene derivative for solution processable organic field-effect transistors. The transistor devices with bottom-contact geometry provided a maximum field-effect mobility of 3.74 x 10(-4) cm2 V(-1) s(-1) as well as current on/off ratio of 5.05 x 10(4) and low threshold voltage. Structural information in the solid state is obtained by thermal analysis and two-dimensional wide angle X-ray scattering (2D-WAXS). From the 2D-WAXS, it is clear that the planes of anthracene rings and benzene ring of the molecule are different in solid state. We assume similar arrangement in the thin-film which limit the effective hopping and thus charge mobility.     

High-frequency graphene voltage amplifier

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ～5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.     

High-performance nano-Schottky diodes and nano-MESFETs made on single CdS nanobelts

Nano-Schottky diodes and nanometal-semiconductor field-effect transistors (MESFETs) on single CdS nanobelts (NBs) have been fabricated and studied. The Au/CdS NB Schottky diodes have very low reverse current density ( approximately 3.0 x 10-5 A.cm-2 at -10 V reverse bias) and the highest on/off current ratio (approximately 108) reported so far for nano-Schottky diodes. The single CdS NB MESFETs exhibit n-channel normally on (depletion) mode, low threshold voltage (approximately -1.56 V), high transconductance ( approximately 3.5 microS), low subthreshold swing ( approximately 45 mV/dec), and the highest on/off current ratio (approximately 2 x 108) reported so far for nanofield-effect transistors. We also show that the absolute value of threshold voltage for a metal-insulator-semiconductor field-effect transistor made on a single CdS NB can be reduced from approximately 12.5 to approximately 0.4 V and its transconductance can be increased from approximately 0.2 to approximately 3.2 microS by adding an extra Au Schottky contact on the CdS NB, the mechanism of which is discussed.     

High-performance logic circuits constructed on single CdS nanowires

A high-performance NOT logic gate (inverter) was constructed by combining two identical n-channel metal-semiconductor field-effect transistors (MESFETs) made on a single CdS nanowire (NW). The inverter has a voltage gain as high as 83, which is the highest reported so far for inverters made on one-dimensional nanomaterials. The MESFETs used in the inverter circuit show excellent transistor performance, such as high on/off current ratio ( approximately 10(7)), low threshold voltage ( approximately -0.4 V), and low subthreshold swing ( approximately 60 mV/dec). With the assembly of three identical NW MESFETs, NOR and NAND gates have been constructed.     

Fully transparent thin-film transistor devices based on SnO2 nanowires

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.     

A radio frequency single-electron transistor based on an InAs/InP heterostructure nanowire

We demonstrate radio frequency single-electron transistors fabricated from epitaxially grown InAs/InP heterostructure nanowires. Two sets of double-barrier wires with different barrier thicknesses were grown. The wires were suspended 15 nm above a metal gate electrode. Electrical measurements on a high-resistance nanowire showed regularly spaced Coulomb oscillations at a gate voltage from -0.5 to at least 1.8 V. The charge sensitivity was measured to 32 microe rms Hz(-1/2) at 1.5 K. A low-resistance single-electron transistor showed regularly spaced oscillations only in a small gate-voltage region just before carrier depletion. This device had a charge sensitivity of 2.5 microe rms Hz(-1/2). At low frequencies this device showed a typical 1/f noise behavior, with a level extrapolated to 300 microe rms Hz(-1/2) at 10 Hz.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.     

Midinfrared injection-pumped laser based on a III–V/II–VI hybrid heterostructure with submonolayer InSb insets

Lasing at 3.075 μm (T = 60 K) in a regime of pulsed injection pumping has been obtained in an AlGaAsSb/InAs/CdMgSe double hybrid heterostructure with the active region comprising an InAs layer with submonolayer InSb insets. The electroluminescence (EL) spectrum of the heterostructure has been studied for various values of the pumping current up to the stimulated emission threshold. An increase in the pumping current leads to a short-wavelength shift and a change in the EL band structure, which is explained by the occupation of higher states by the charge carriers in InSb quantum dots and/or in the adjacent InAsSb layer.     

SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec^?1 at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS₂ van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS₂ vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS₂ as the channel, the SnSe/MoS₂ vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltage V_P of ?0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec^?1 and high ON/OFF ratio over 10⁶, demonstrating excellent electronic performance especially in the subthreshold regime.     

Uniform and position-controlled InAs nanowires on 2" Si substrates for transistor applications

This study presents a novel approach for indirect integration of InAs nanowires on 2' Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2' Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2' wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.     

Focused ion beam creation and templating of InAs and InAs/InP nanospikes

Ion beam irradiation has been examined as a method for creating nanoscale semiconductor pillar and cone structures, but has the drawback of inaccurate nanostructure placement. We report on a method for creating and templating nanoscale InAs spikes by focused ion beam (FIB) irradiation of both homoepitaxial InAs films and heteroepitaxial InAs on InP substrates. These 'nanospikes' are created as In droplets, formed due to FIB irradiation, act as etch masks for the underlying InAs. By pre-patterning the InAs to influence In droplet movement, nanospike locations on homoepitaxial InAs may be controlled with limited accuracy. Creating nanospikes using an InAs/InP heterostructure provides an additional measure of control over where the spikes form because nanospikes will not form on exposed regions of InP. This effect may be exploited to accurately control nanospike placement by pre-patterning an InAs/InP heterostructure to control the location of the InAs/InP interface. Using this heterostructure templating method it is possible to accurately place nanospikes into regular arrays that may be useful for a variety of applications.     

A Very Low Offset Preamplifier for Voltage Measurements in the $muhbox{V}$ Range

A new topology for the implementation of a very low offset voltage preamplifier is presented. The new topology employs a time-varying resistance as a probe for detecting the sign and magnitude of the equivalent input offset of an operational amplifier in a series-shunt feedback configuration and allows for continuously correcting the offset voltage by means of a proper control feedback. The most remarkable feature of the approach we propose is the fact that the offset correction can continuously be performed with the signal voltage source connected to the circuit, as its presence and magnitude do not affect the offset detection circuit. At the same time, the offset cancellation circuit has minimum effect on the output voltage of the preamplifier in the bandwidth of the signal. An actual low-offset preamplifier based on the new approach we propose has been built and tested. While employing a metal–oxide–semiconductor field-effect transistor (MOSFET) input operational amplifier with a typical input offset of 100 $muhbox{V}$ (600- $muhbox{V}$ maximum), a voltage preamplifier with a gain of 201 and an equivalent input offset voltage below 100 nV is consistently obtained, which is independent, by design, of the temperature. While characterized by these excellent performances, the system employs quite standard low-cost components and does not require any calibration procedure.      

InAs/InP radial nanowire heterostructures as high electron mobility devices

Radial core/shell nanowires (NWs) represent an important class of one-dimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum-confined, high-mobility electron carriers. Transmission electron microscopy studies revealed single-crystal InAs cores with epitaxial InP shells 2-3 nm in thickness, and energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed heterostructure. Room-temperature electrical measurements on InAs/InP NW field-effect transistors (NWFETs) showed significant improvement in the on-current and transconductance compared to InAs NWFETs fabricated in parallel, with a room-temperature electron mobility, 11,500 cm(2)/Vs, substantially higher than other synthesized 1D nanostructures. In addition, NWFET devices configured with integral high dielectric constant gate oxide and top-gate structure yielded scaled on-currents up to 3.2 mA/microm, which are larger than values reported for other n-channel FETs. The design and realization of high electron mobility InAs/InP NWs extends our toolbox of nanoscale building blocks and opens up opportunities for fundamental and applied studies of quantum coherent transport and high-speed, low-power nanoelectronic circuits.     

Correlated Variation of Electrical Characteristics of a Thin-Film Field-Effect Transistor during Modification of the Physical Properties of an InZnO:N Oxide Semiconductor Channel

Technical Physics Letters - We have studied changes in the transmission and current–voltage characteristics of a thin-film field-effect transistor (TFT) during modification of the physical...     

Photodiodes based on InAs/InAsSb/InAsSbP heterostructures with quantum efficiency increased by changing directions of reflected light fluxes

It is shown, using the example of InAs/InAsSb/InAsSbP heterostructures, that the formation of a curvilinear reflecting surface consisting of hemispherical etch pits on the rear side of a photodiode chip leads to an increase in the quantum efficiency of photodiodes by a factor of 1.5–1.7 in the entire mid-IR wave-length interval studied (λ = 3–5 μm). For the obtained photodiodes with a cutoff wavelength of 4.8 μm, a photosensitive area of 0.1 mm², and a chip area of 0.9 mm², a monochromatic responsivity at λ = 4.0 μm reached 0.6 A/W, while a dark current at a reverse bias voltage of 0.2 V was within 4–6 A/cm².     

Device modeling of ferroelectric memory field-effect transistor for the application of ferroelectric random access memory

An improved theoretical analysis on the electrical characteristics of ferroelectric memory field-effect transistor (FeMFET) is given. First, we propose a new analytical expression for the polarization versus electric field (P-E) for the ferroelectric material. It is determined by one parameter and explicitly includes both the saturated and nonsaturated hysteresis loops. Using this expression, we then examine the operational properties for two practical devices such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) as well. A double integral also has been used, in order to include the possible effects due to the nonuniform field and charge distribution along the channel of the device, to calculate the drain current of FeMFET. By using the relevant material parameters close to the (Bi, La)/sub 4/Ti/sub 3/O/sub 12/ (BIT) system, accurate analyses on the capacitors and FeMFET's at various applied biases are made. We also address the issues of depolarization field and retention time about such a device.