低阻硅CMOS工艺片上互连线模型

提出了一种新的互补金属氧化物半导体(CMOS)工艺片上的互连线模型,模型在考虑互连线金属导体高频效应和衬底效应的基础上,引入了一个电容来表征金属导体通过氧化层在低阻硅衬底中引起的容性耦合特性.建立的互连线模型通过0.18 μm CMOS工艺上制作的互连线测试数据验证,频率精度可至50 GHz.     

一种高频无源元件的EM建模分析技术

采用电磁场(EM)建模的分析方法,提取了砷化镓衬底上MIM电容、方形螺旋电感和微带传输线的等效电路模型,并应用于一种π形匹配网络的设计,该模型充分考虑了衬底损耗、趋肤效应、接近效应等因素,对无源元件电特性的影响,基于GaAs半导体工艺进行了流片.测试结果表明,在0.1～40 GHz频率范围内,采用EM技术提取的元件参数...     

两相邻耦合互连的Elmore延时估计

基于"有效电容"的概念提出了一种分析两相邻耦合RC互连延时的方法.与采用Miller电容的传统方法比较,该方法不但提高了计算精度而且反映出了延时随信号上升时间的变化规律.该方法与Elmore延时法具有相同的计算复杂度,可广泛用于考虑耦合电容的面向性能的布线优化.     

Elmore Delay Estimation of Two Adjacent Coupling Interconnects

基于"有效电容"的概念提出了一种分析两相邻耦合RC互连延时的方法.与采用Miller电容的传统方法比较,该方法不但提高了计算精度而且反映出了延时随信号上升时间的变化规律.该方法与Elmore延时法具有相同的计算复杂度,可广泛用于考虑耦合电容的面向性能的布线优化.     

异质互连通孔等效电路模型及其特性分析

考虑了三维异质集成系统中不同衬底层对通孔产生的寄生效应,分别提出了应用于单个和一对差分异质互连通孔的宽频带等效电路模型.在所提出的模型中,Csub和Gsub分别表征衬底耦合效应,Lm、Cm和Gm分别表征两个通孔之间的耦合效应.通过验证,模型在150 GHz频带范围内都具有较高的精度.基于所提出的模型,对单个和一对差分互...     

90 nm CMOS工艺下串扰延迟及其测量电路的研究

仿真分析了90 nm CMOS工艺中串扰延迟的趋势,结果表明,90 nm CMOS工艺下1 mm的连线延迟远大于单位门的延迟,最坏情况下1 mm连线延迟约为单位门延迟的6倍,而当线间耦合电容发生作用时,串扰延迟在连线延迟中起主要作用.提出了一种用于测量超深亚微米工艺串扰延迟的新型电路,电路主要由VCO和几个触发器组成,采用HSPICE对电路进行了仿真,结果表明所提出的电路最大测量误差为1.33%.     

基于"有效电容"的耦合RC互连延时分析

本文在保证互连延时特性不变的基础上将两相邻耦合RC互连中的耦合电容和静态互连电路等效为一“有效电容”,并将其用于有源互连的Elmore延时计算。与传统的采用Miller电容的方法进行了比较,它不但提高了计算精度而且反映了延时随信号上升时间变化的规律。本文方法与Elmore延时具有相同的计算复杂度,可广泛用于考虑耦合电容的面向性能的布线优化。     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

硅衬底片上螺旋电感宽带2π等效电路模型

针对高损耗硅衬底,基于部分元等效电路方法和全耦合变压器模型,建立了一种新的片上螺旋电感物理模型.该模型考虑了趋肤效应、邻近效应和衬底涡流损耗对螺旋电感中串联电感和串联电阻频率特性的制约,并通过2π等效电路结构计入了电感中寄生电容的分布特性.通过与全波分析方法对比,验证了在15GHz范围内由该模型导出的等效电感、等效电阻和Q值误差均在8%以内.该模型可望用于硅基射频集成电路中电感的优化设计和进一步的理论探讨.     

A transistor performance figure-of-merit including the effect ofgate resistance and its application to scaling to sub-0.25-μm CMOSlogic technologies

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25-μm CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet resistance requirement is derived from the new FOM. Using this expression, requirements on the gate sheet resistance are calculated corresponding to a technology roadmap for performance and oxide thickness     

Delay calculation capturing crosstalk effects due to coupling capacitors

A driver model to calculate gate and interconnect delays accurately for a chip with coupling capacitors is presented. The crosstalk effects between simultaneously switching victim and aggressors are effectively captured by iteratively solving an N-port RC network. The algorithm was implemented in a delay calculation tool called XINT and its accuracy demonstrated for industrial designs.     

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.     

Hybrid Aging Delay Model Considering the PBTI and TDDB

With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB) effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBTI and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

TFT AMLCD像素矩阵电路中栅延迟的模拟研究

建立了ａ－ＳｉＴＦＴＡＭＬＣＤ的等效电路模型,综合考虑栅信号线电阻、栅与源信号线的交叠电容以及ＴＦＴ导电沟道电容构成的ＲＣ（ＲｅｓｉｓｔｉｖｉｔｙＣａｐａｃｉｔａｎｃｅ）常数,模拟计算了栅信号延迟对液晶显示屏尺寸、显示分辨率及栅信号电极材料的依赖关系,为实现器件优化设计提供参考。     

VDSM集成电路互连特性及RC延迟研究

利用多层金属导体寄生电容模型,详细分析了不同的金属互连线参数对寄生电容的影响,并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计.结果表明,当金属导线的纵横比接近2时,线间耦合电容对互连总电容的影响将占主导地位.在超深亚微米工艺条件下,当金属线宽和间距比例W/P的最优质值为0.5～0.6时,计算的互连延迟为最小.此外,还给出了低介电常数材料对互连线电容和延迟的影响,为超深亚微米级的集成电路设计与实现提供有益的参考.     

超深亚微米CMOS工艺参数波动的测量电路

分析了超深亚微米工艺参数波动对电路的影响;采用"放大"的思路设计了简单的用于测量超深亚微米工艺门延迟、动态功耗、静态功耗及其波动的电路,并提出了一种用于测量门延迟波动特性曲线的新型电路,该电路采用较短的反相器链可以得到超深亚微米工艺下门延迟波动特性曲线.电路在90nm CMOS工艺下进行了流片制作,得到了90nm CMOS工艺下的单位门延迟波动特性曲线.测得延迟的波动范围为78.6%,动态功耗的波动范围为94.0%,漏电流功耗的波动范围为19.5倍,其中以漏电流功耗的波动性最为严重.