High-voltage DMOS integrated circuits using floating-gate protection technique

An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level shifting involves complex circuits that reduce the speed besides requiring of large power and area. In this paper, a simple and efficient protection technique for gate-oxide breakdown is achieved by connecting a capacitor divider structure to the floating-gate node of HV transistor to increase its effective gate oxide thickness. Several HV circuits, including: positive and negative HV doublers and level-up shifters suitable for ultrasound sensing systems are built successfully around the proposed technique. These circuits were implemented with 0.8 μm CMOS/DMOS HV DALSA process. Simulation and experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 200 V.     

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)     

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology

On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters.     

Fully Integrated High-Voltage Front-End Interface for Ultrasonic Sensing Applications

This paper concerns the design and implementation of a fully integrated high-voltage (HV) front-end transducer for ultrasonic sensing applications. This includes a programmable HV dc-dc converter (HVDC), a drive amplifier, and a tuneable pulse generator. The HVDC is based on a multistage two-phase voltage doubler and static level up shifters. The drive amplifier is composed of a static level-up stage and a Class-D switching output stage. Post-layout simulation and experimental silicon results are reported for two HVDC stages and a drive amplifier, which were fabricated using a 0.8-mum CMOS/DMOS process and having a supply voltage of 5 V/400 V. The measurement results confirm the validation of the HV circuit implementation and its design optimization. An output voltage of up to 200 V was obtained from the HVDC. Also, the drive amplifier generates spikes up to 148 V, with rise and fall times of 69 and 58 ns, respectively. The peak current flowing through the transducer element can be as high as 200 mA     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Summary  Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 μm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 μm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 μm HVCMOS technology to 0.18 μm and beyond as well as to currents of up to 8 A.      

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

An analytical model with flexible accuracy for deep submicron DCVSL cells

Differential cascoded voltage switch logic (DCVSL) cells are among the best candidates of circuit designers for a wide range of applications due to advantages such as low input capacitance, high switching speed, small area and noise-immunity; nevertheless, a proper model has not yet been developed to analyse them. This paper analyses deep submicron DCVSL cells based on a flexible accuracy-simplicity trade-off including the following key features: (1) the model is capable of producing closed-form expressions with an acceptable accuracy; (2) model equations can be solved numerically to offer higher accuracy; (3) the short-circuit currents occurring in high-low/low-high transitions are accounted in analysis and (4) the changes in the operating modes of transistors during transitions together with an efficient submicron I-V model, which incorporates the most important non-ideal short-channel effects, are considered. The accuracy of the proposed model is validated in IBM 0.13 µm CMOS technology through comparisons with the accurate physically based BSIM3 model. The maximum error caused by analytical solutions is below 10%, while this amount is below 7% for numerical solutions.     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion. The improved Miller OTA has been successfully verified in a standard 0.35-mum CMOS process. Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.     

一种基于BCD工艺的高速低功耗电平位移电路

提出了一种基于0.25 μm BCD工艺、适用于高压降压型DC-DC转换器的新型电平位移电路.该电路使用了耐压60 V的高压DMOS器件(HVNMOS、HVPMOS)、耐压5V的低压CMOS器件(LVNMOS、LVPMOS),以及耐压5V的三极管器件(BJT).分析了降压型DC-DC转换器对电平位移电路的特殊要求;基于对两种常见电平位移电路的分析,提出了一种新型的电平位移电路.电路仿真结果显示,与之前的电路相比,新型电路结构具有响应快速、功耗低、输出电平精确、可靠性高等优点.     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

Evolution of a CMOS Based Lateral High Voltage Technology Concept

This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.V_GS=max.V_DS=3.3V, max.V_GS=max.V_DS=5.5 V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35 μm CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.     

PDP选址驱动芯片的HV-COMS器件设计

设计出一种能与 0 .6μm的标准低压 CMOS工艺完全兼容的 HV-CMOS (High Voltage CMOS)结构 ,并提出了具体的工艺实现方法——单阱非外延工艺 ,该工艺能降低生产难度和成本。同时采用 TSUPREM-4对该结构进行工艺模拟 ,并用 MEDICI对该结构的电流 -电压和击穿等特性进行模拟。该结构的 HV-CMOS应用于 PDP(Plasma Display Panel)选址驱动芯片 ,能在 80 V、40 m A的工作要求下安全工作     

Low-voltage-swing monolithic dc-dc conversion

A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter.     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

0.15-μm RF CMOS technology compatible with logic CMOS forlow-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications     

基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器

实现了一种10位2.5MS/s逐次逼近A/D转换器。在电路设计上采用了R-C混合结构D/A转换、伪差分比较结构以及低功耗电平转换方式实现。为了实现好的匹配性能,在版图布局上分别采用电阻梯伪电阻包围对策以及电容阵列共中心对称布局方式进行布局。整个A/D转换器基于90nm CMOS工艺实现,在3.3V模拟电源电压以及1.0V数字电源电压下,测得的DNL和INL分别为0.36LSB和0.69LSB。在采样频率为2.5MS/s,输入频率为1.2MHz时,测得的SFDR和ENOB分别为72.86dB和9.43bits。包括输出驱动在内,测得整个转换器的功耗为6.62mW。整个转换器的面积约为238um×214um。设计结果显示该转换器性能良好,非常适合多电源嵌入式SoC的应用。