Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

Asymptotic behavior of periodicH ∞ a posteriori filters

The asymptotic behavior of linear periodic discrete-timeH a posteriori filters is discussed in this paper. We extend existing results for time-invariantH filters to study the problems arising from periodic discrete-time systems. Based on quasi-lifting techniques, a sufficient condition for ensuring feasibility and convergence ofH a posteriori filters is given.     

High Dynamic Range Design for ΣΔM with Wide Input Ranges

A new design algorithm is introduced to improve the input ranges of Sigma-Delta Modulation (M). Modified digital error correction techniques are proposed and employed to carry out the wide range DAC of a modulator. This design algorithm includes the advantages from both single-bit M and multi-bit M. This paper utilizes a second order lowpass modulator as an explanatory example to demonstrate our design process as well as the performance improvement. The analytical results from a quasilinear model are described to offer a theoretical explanation of the system performance. This algorithm can also be applied to bandpass and MASH architectures.     

Optimization and Design of a Low Power Switched Current A/D-ΣΔ-Modulator for Voice Band Applications

This paper presents a third order switched current -modulator. The modulator is optimized at the system level for minimum power consumption by careful design of the noise transfer function. A thorough noise analysis of the cascode type current copiers used to implement the modulator, together with a new methodology for evaluating the nonlinear settling behavior is presented. This leads to a new optimization methodology that minimize the power consumption in switched current circuits for given design parameters. The optimization methodology takes process variations into account. The modulator is implemented in a standard 2.4 m CMOS process only using MOS capacitors. For a power supply of 3.3 V the power consumption is approximately 2.5 mW when operating at a sampling rate of 600 kHz. Under these condition the peak SNR it measured to 74.5 dB with a signal band width of 5.5 kHz. Due to internal clamping in the integrators and proper scaling the modulator shows excellent stability properties. In order to compare the performance of the modulator presented in this paper to other -modulators two figure-of-merits (FOMs) are proposed. From these figure-of-merits it is found that the performance of the modulator presented in this paper is significantely higher than the perforamce of other switched current -modulators reported. Also, the figure-of-merits show that the performance is comparable to the performance of reported switched capacitor -modulators.     

Symmetry relations in multidimensional Fourier transform pairs

A relation between the types of symmetries that exist in signal and Fourier transform domain representations is derived for continuous as well as discrete domain signals. The symmetry is expressed by a set of parameters, and the relations derived in this paper will help to find the parameters of a symmetry in the signal or transform domain resulting from a given symmetry in the transform or signal domain respectively. A duality among the relations governing the conversion of the parameters of symmetry in the two domains is also brought to light. The application of the relations is illustrated by a number of two-dimensional examples.Notation R the set of real numbers - R ^m R × R × ... × R m-dimensional real vector space - continuous domain real vector - L {¦ – _i , i = 1,2,..., m} - m-dimensional frequency vector - W { – _i ,i=1,2,..., m} - m-dimensional normalized frequency vector - _P {¦ – _i , i=1,2,...,m} - g(ol) g (₁,₂,..., _m ) continuous domain signal - () ( _{1 2},..., _m )=G (j ₁,j ₂,..., j _m ) Fourier transform ofg (ol) - (A,b,,,) parameters ofT- symmetry - N the set of integers - N ^m N × N × ... × N m-dimensional integer vector spacem-dimensional lattice - h(n) h (n ₁,.,n _m ) discrete domain signal - H() Fourier transform ofh (n) - v ₁,v ₂,..., v_m m sample-direction and interval vectors - V (v ₁ v ₂ ...v _m ) sampling basis matrix - [x]^* complex conjugate ofx - detA determinant ofA - X {x¦ – x _i , i=1,2,..., m} - A ^–t [A ^–1] ^t ,t stands for transpose This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant A-7739 to M. N. S. Swamy and in part by Tennessee Technological University under its Faculty Research support program to P. K. Rajan.     

Using a WLFSR to Embed Test Pattern Pairs in Minimum Time

We propose a methodology for reducing the number of test cycles needed by a Weighted LFSR (WLFSR) to reproduce a 2P × W test matrix T of P pattern pairs. The methodology introduces a very small number of extra cells into the WLFSR and uses appropriate combinational mapping logic in order to make the time be equal to that required by a (W + )-bit WLFSR to generate vectors containing the W bits of the first pattern for each pair plus the extra bits. We present an algorithm that makes the value of be less than or equal to log₂, where is the size of the maximum subset of pairs in T with identical first patterns. This is a significant improvement over the time E _P,W · P required by a trivial approach that uses a WLFSR with W cells to generate the first patterns of the pairs and a P × W ROM to store the second patterns of the pairs. Experimental results on the application of the methodology to the embedding of test matrices for path delay faults are particularly encouraging, even for very large numbers of test pattern pairs that are necessary for provably high fault coverage.     

Geometric properties of nonlinear networks containing capacitor-only cutsets and/or inductor-only loops. Part I: Conservation laws

This paper is the first in a two part sequence which studies nonlinear networks, containing capacitor-only cutsets and/or inductor-only loops from the geometric coordinate-free point of view of differentiable manifolds. Given such a nonlinear networkN, with °₀ equal to the sum of the number of independent capacitor-only cutsets and the number of independent inductor-only loops, we establish the following: (i) circuit theoretic sufficient conditions to guarantee that the set ⁰, of equilibrium points is a ₀-dimensional submanifold of the state space ofN; (ii) circuit theoretic sufficient conditions for the condition thatN has ₀ independent conservation laws and hence that through each point of the state space ofN, there passes a codimension ₀ invariant submanifold ^* of the network dynamics; (iii) circuit theoretic sufficient conditions to guarantee that the manifolds ^* and ⁰ intersect transversely.This work was supported by the Natural Sciences and Engineering Research Council of Canada, under Grant Number A7113, and by scholarships from the Natural Sciences and Engineering Research Council of Canada and the Ontario Provincial Government.     

Bilateral polynomial matrix equations in two indeterminates

Two special cases of the bilateral 2-D polynomial matrix equationDU +VN=C whenC=I andC=I with being a -stable 2-D polynomial, which are related respectively to deadbeat and asymptotic control problems of 2-D systems, are first considered. By generalizing the concepts of factor coprimeness, zero coprimeness and zero skew primeness in the 2-D polynomial ring to the ring of causal -stable 2-D rational functions, a constructive solution of these two problems mentioned is proposed. Based on these results, we derive a solvability condition for the bilateral equiation whereC is a general 2-D polynomial matrix. The general solutions are investigated as well.     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

Conservative Input–State–Output Systems with Evolution on a Multidimensional Integer Lattice

A fundamental object of study in both operator theory and system theory is a discrete-time conservative system (variously also referred to as a unitary system or unitary colligation). In this paper we introduce three equivalent multidimensional analogues of a unitary system where the time axis , d>1, is multidimensional. These multidimensional formalisms are associated with the names of Roesser, Fornasini and Marchesini, and Kalyuzhniy–Verbovetzky. We indicate explicitly how these three formalisms generate the same behaviors. In addition, we show how the initial-value problem (including the possibility of initial conditions at infinity) can be solved for such systems with respect to an arbitrary shift-invariant sublattice as the analogue of the positive-time axis. Some of our results are new even for the d=1 case.First online version published in May 2005*The authors were supported in part by a grant from the US-Israel Binational Science Foundation.     

Linear phase FIR approximation of magnitude response |1/ω| for maximal flatness at an arbitrary frequency ω0, 0<ω0<π*

In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function: (a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency ₀ in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of are known in the literature. This paper suggests a design by which the linear phase magnitude response can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency ₀, 0<₀<^*. A technique to compute exact weights for the design has also been given.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Parametric toeplitz systems

This paper investigates the properties of the two-variable polynomialu (, z) built on the first column of the adjoint matrix ofI -C, whereC is a given Hermitian Toeplitz matrix. In particular, the stability properties ofu (,z) are discussed and are shown to depend essentially on the location of X with respect to the eigenvalues ofC. The eigenvectors ofC, which have recently found some applications in signal processing and estimation theory, are obtained from the polynomialu(,z) when tends to the eigenvalues ofC. This allows one to derive several results concerning the eigenpolynomials, including those for the case of multiple eigenvalues.     

The Card Services Platform — rapid delivery of giant systems

This paper describes the top-level integration strategy for delivering the Card Services Platform (CSP), formerly known as Cashless Services Replacement System (CSRS), probably the largest successful integration by a single BT team to date. This paper explains the need for such a strategy to evolve, leading to significant efficiency improvements. It identifies the need for the careful management of integration testing of the complex interfaces involved in a system comprised of over 40 large computer systems, spread across the country. It shows how potential operational difficulties can be identified in the system testing phase and eradicated before impacting the product in a live situation. It outlines testing techniques, test coverage, granularity of test results and measure of goodness of the tested product.     

Theory of PLL fractional-N frequency synthesizers

This paper presents an overview of the evolution of frequency synthesizers based on phase-locked loops (PLLs). The main limitations of the digital PLLs are described, and the consequent necessity of using fractional-N techniques is justified. The origin of the typical spurious noise lines on the sidelobes of the synthesized frequency is explained. It is shown how to eliminate these spurious noise lines by using digital modulators to control the frequency division value. Finally, the implications of using digital modulators together with fractional-N PLLs on the output phase noise are analysed.     

Redundancy Removal during High-Level Synthesis Using Scheduling Don‘t-Cares

Previous work in automata theory has shown how to eliminate sequential redundancy from networks of FSMs by finding sequences of inputs and outputs which are never communicated between components of the network. This paper shows that behavior automata—finite-state machines whose inputs and outputs are incompletely scheduled—exhibit similar properties. Using the behavior FSM (BFSM) as a model for scheduling, we show how to identify and eliminate both input and output scheduling dont-cares. When a scheduling dont-care is eliminated from a network of BFSMs, the register-transfer implementation is guaranteed not to suffer from the corresponding dont-care sequence. A definition of scheduling dont-cares improves our understanding of the foundations of high-level synthesis and the relationship between high-level and sequential optimization. In practice, scheduling dont-care elimination is a powerful tool for eliminating redundancy early in the design process.     

Solutions for H∞ Filtering of Two-Dimensional Systems

Thispaper deals with the H filtering problemfor linear discrete-time two-dimensional (2-D) systems describedby the Roesser model. It firstly establishes a version of thebounded real lemma to give a sufficient condition for quantificationof the H noise attenuation for 2-D systems.Based on the bounded real lemma, the H filteringproblem is investigated for filters of an observer-based structureor a general state equation form and the solutions are obtainedin terms of Riccati inequalities or linear matrix inequalities.The design approach is illustrated by an example of a stationaryfield in image processing.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Performance Monitoring for In-life Capacity Management

The key to providing a meaningful management view of the performance of complex systems lies in having a co-ordinated process for data collection, analysis and presentation. TeleMarketing Services, such as the Freefone service, provide a good example. Managers of diverse, remote subsystems receive summarised performance and customer service information, mostly in the form of simple graphs, in exchange for providing reliable data. The aim is to bring together a structured view of all the components, including a red-amber-green status table, for use by senior customer-facing staff. Generally, the analyses focus on capacity, forecast and measurement, covering a flexible range of parameters. Managers then have an early view of service degradation, potential capacity exhaustion, workload imbalance and resource wastage, enabling timely remedial action, fault clearance and system enhancements.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.