低功耗方法在SoC芯片设计中的应用

SOC芯片设计在集成电路设计中占据重要位置,低功耗设计是SoC设计过程中的重要环节。本文首先全面分析了CMOS电路的功耗组成和功耗估计的相关理论,随后从各个设计层次详细分析了SOC芯片低功耗设计的理论及其实现方法。     

百万门级系统芯片低功耗技术研究

针对超大规模集成电路低功耗设计技术市场需求的迅速增大,提出了一种新的百万门级系统芯片低功耗设计流程,重点分析了芯片系统级、电路级、逻辑级与物理级四个不同的层次的低功耗设计方法,包括系统构架、时钟与功耗管理算法等低功耗关键技术。以某新型雷达SoC低功耗设计为例,采用SMIC 0.18 μm 1P6M CMOS工艺进行设计,版图尺寸为7.825 mm×7.820 mm,规模约为200万门。实验结果表明,在100 MHz工作频率下,采用新的低功耗设计流程后,前端设计阶段功耗降低了42.79%,后端设计阶段功耗降低了12.77%,芯片总功耗仅为350 mW。样品电路通过了用户某新型相控阵雷达系统的应用验证,满足小型化和低功耗的要求。     

深亚微米工艺下系统芯片低功耗技术

功耗问题将成为系统芯片发展的一个瓶颈.影响深亚微米工艺下系统芯片的功耗因素比较多,论文从不同的层次对功耗进行分析,找到影响电路功耗的主要因素.对系统芯片而言,其电路规模比较大,工作模式复杂、工作速度较高,因此全面降低芯片功耗是设计者在规划时就必须考虑的重要因素.文中以实际设计的系统芯片为例,从系统级、电路级、逻辑级等不...     

SoC门级功耗分析方法

随着IC设计规模的增大和运行频率的提高,设计中低功耗的需求也随之提高,在芯片投片之前,能够比较准确的评估出芯片的功耗是当前设计中非常关键的技术点之一。比较四种不同层次的功耗分析方法,门级功耗分析兼有精度高,分析速度快的优点。根据SPI接口电路实践,描述了门级功耗工具的使用方法,并通过门级和晶体管级分析的对比测试证明该方法能较为准确的估算出新品的功耗,为SoC项目的正常研发提供帮助。     

一种SoC低功耗模式设计与实现

为降低芯片功耗,提升性能,从系统级、结构级和RTL级3个层次提出了一种片上系统(System on Chip,SoC)芯片的低功耗设计方法,并在样片中得以验证。在系统级层面,根据SoC芯片的不同工作场合,在正常运行模式的基础之上,设计了睡眠、停止和待机3种低功耗模式。在结构级层面,将整个芯片划分为VDD、VDDA和VBAT3个电压域,以降低系统功耗。在RTL级,针对不同的模式切换,设计了时钟管理技术,实现了对不同模式下不同时钟的控制。仿真和实验结果证明了设计的合理性,实测数据表明,睡眠模式最多降低59.1%的功耗,停止和待机模式降低了3~4个数量级。     

多媒体SOC芯片的低功耗设计

从集成电路功耗原理出发,分析了CMOS电路功耗的来源,从集成电路设计的系统级、算法级、架构级、电路/门级以及工艺/器件级五个抽象层次出发,整理、总结了当前主要的低功耗设计方法,并在实际的移动多媒体处理应用SOC芯片设计中,平衡产品成本、设计复杂度、设计环境等多种因素,确定并应用了适合设计对象的低功耗设计方法的组合.通过对于样片功耗的测试分析,低功耗设计方法(组合)取得了预期的效果,实现了较低的动态功耗与很低的静态功耗.     

SOC时代低功耗设计的研究与进展

在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向.     

一种低功耗时钟芯片的设计与实现

本文讨论了一种低功耗时钟芯片的设计与实现。通过分析CMOS电路功耗产生原因,给出了详细的低功耗实现方案。流片后测试表明该芯片工作电流0.17mA,满足低功耗要求。     

基于SOC的低功耗管理模块设计

功耗是片上系统(SOC)设计中的关键指标之一。对于SOC芯片的低功耗设计,可以采用多种设计方法进行优化。本文设计的低功耗管理模块是通过管理工作时钟的方式对SOC的功耗进行动态调节,能够有效地降低SOC芯片的功耗。     

TD-LTE手机低功耗模式的选择

低功耗设计是大部分手持嵌入式设备必须考虑的一点,也是评定整个系统性能的重要指标之一。TD—LTE移动终端低功耗设计是一个系统的问题,它涉及到不同层次中对低功耗的考虑．比如通信协议、操作系统、硬件电路等在低功耗设计中都涉及到不同的控制方法。文章主要对低功耗控制模式进行功耗分析对比,从而对低功耗模式进行科学合理的划分。     

CMOS数字电路功耗分析及其应用

讨论了有关ＣＭＯＳ数字电路的功耗分析和低功耗逻辑综合的一些方法。研究了信号的翻转概率与信号概率之间的关系，并由此得到信号翻转次数的表达式。然后讨论了使平均功耗最优的组合逻辑电路优化中的一些方法，最后，提出了两个用于低功耗逻辑综合的基本定理。     

Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

The greatinformation processing power of human being' s neural systems has attract-ed a lotof attention of those who are dedicated to the implementation of Artificial NeuralNetworks(ANNs) ,which are expected to be of the same computat...     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.     

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.     

Design techniques for low-voltage high-speed digital bipolarcircuits

This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-μm 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-μm CMOS process with zero threshold voltage     

纳米集成电路静态功耗机理及低功耗设计技术

对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述．以期为相关研究：设计人员提供有益参考。     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance